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Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Akira Nagoya (Okayama Univ.)
Vice Chair Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.)
Secretary Yohei Hori (AIST), Tomonori Izumi (Ritsumeikan Univ.)
Assistant Nobuya Watanabe (Okayama Univ.)

Conference Date Thu, Sep 16, 2010 11:00 - 18:35
Fri, Sep 17, 2010 09:00 - 14:05
Topics Reconfigurable Systems, etc. 
Conference Place Shizuoka University Faculty of technology Electric electronics building 
Address 3-5-1, Johoku, Hamamatsu-shi, Shizuoka-ken, 432-8561
Transportation Guide JR Central Hamamatsu Station kitaguchi Entetsu bus stop: -- bus terminal 15 or 16 -- all the route stop at Shizuoka University (15 minutes ride).
Prof. Minoru Watanabe, Shizuoka University
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)

Thu, Sep 16 AM 
11:00 - 11:50
(1) 11:00-11:25 Development of an On-chip Pattern Recognition System using Dynamic and Partial Reconfiguration RECONF2010-18 Hiroyuki Kawai, Moritoshi Yasunaga (Tsukuba Univ.)
(2) 11:25-11:50 Real-time detection of line segments on FPGA RECONF2010-19 Jianyun Zhu, Tsutomu Maruyama (Univ. of Tsukuba)
  11:50-12:50 Lunch Break ( 60 min. )
Thu, Sep 16 PM 
13:00 - 14:15
(3) 13:00-13:25 A Regular Expression Matching Circuit Based on an NFA with Multi-Character Consuming RECONF2010-20 Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura (KIT)
(4) 13:25-13:50 Finite Field Arithmetic on a Reconfigurable Processor with Variable Word Size RECONF2010-21 Yuichiro Shibata, Ryuichi Harasawa, Kiyoshi Oguri (Nagasaki Univ.)
(5) 13:50-14:15 A Consideration of Reconfigurable Processor for RSA Cryptography RECONF2010-22 Takatoshi Tamaoki, Kazuya Tanigawa, Tetsuo Hironaka (hcu)
  14:15-14:35 Break ( 20 min. )
Thu, Sep 16 PM 
14:35 - 15:50
(6) 14:35-15:00 Accelerating HMMER search using FPGA Grid RECONF2010-23 Toyokazu Takagi, Tsutomu Maruyama (Tsukuba Univ.)
(7) 15:00-15:25 Hardware Lossless-Compressors of Floating-Point Data Streams to Enhance Memory Bandwidth RECONF2010-24 Kentaro Sano, Kazuya Katahira, Satoru Yamamoto (Tohoku Univ.)
(8) 15:25-15:50 Evaluation of Multiple-Precision Floating-Point Accelerator HP-DSFP through Applications. RECONF2010-25 Yuki Yoshioka, Tomoyuki Kawamoto, Taiga Ban, Kazuya Tanigawa, Tetsuo Hironaka (HCU)
  15:50-16:10 Break ( 20 min. )
Thu, Sep 16 PM 
16:10 - 17:25
(9) 16:10-16:35 An SA-based Placement and Routing Method Considering Cell Congestion for MPLDs RECONF2010-26 Masatoshi Nakamura, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (TAIYO YUDEN)
(10) 16:35-17:00 Design and Implementation of a Layout Tool for the MPLD Architecture RECONF2010-27 Ken Taomoto, Hideyuki Kawabata, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura (Hiroshima City Univ.)
(11) 17:00-17:25 A Peformance Estimation Method for Dynamically Reconfigurable Architecture in Stream Processing RECONF2010-28 Fumihiko Hyuga, Takashi Yoshikawa (Toshiba)
  17:25-17:45 Break ( 20 min. )
Thu, Sep 16 PM 
17:45 - 18:35
(12) 17:45-18:35 [Invited Talk]
Applications of optically reconfigurable gate arrays RECONF2010-29
Minoru Watanabe (Shizuoka Univ.)
Fri, Sep 17 AM 
09:00 - 10:40
(13) 09:00-09:25 A MEMS addressing technique in optically reconfigurable gate arrays RECONF2010-30 Hironobu Morita, Minoru Watanabe (Shizuoka Univ.)
(14) 09:25-09:50 COGRE: A Novel Compact Logic Cell Architecture for Area Reduction RECONF2010-31 Yasuhiro Okamoto, Yoshihiro Ichinomiya, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(15) 09:50-10:15 An Error Detect and Correct Circuit Based Fault-tolerant Reconfigurable Logic Device RECONF2010-32 Qian Zhao, Yoshihiro Ichinomiya, Yasuhiro Okamoto, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)
(16) 10:15-10:40 Structure of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture RECONF2010-33 Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama (Tohoku Univ.)
  10:40-11:00 Break ( 20 min. )
Fri, Sep 17 AM 
11:00 - 12:15
(17) 11:00-11:25 Removing context memory from Multi-context Dynamically Reconfigurable Processors RECONF2010-34 Hideharu Amano, Masayuki Kimura, Nobuaki Ozaki (Keio Univ.)
(18) 11:25-11:50 Power reduction for Dynamically Reconfigurable Processor Array with reducing the number of reconfiguration RECONF2010-35 Masayuki Kimura, Kazuei Hironaka, Hideharu Amano (Keio Univ.)
(19) 11:50-12:15 Performance Evaluation of the SIMD/MIMD Dynamic Mode Switching Processor IMAPCAR2 RECONF2010-36 Shorin Kyo, Shohei Nomoto, Shinichiro Okazaki (RE)
  12:15-13:15 Lunch Break ( 60 min. )
Fri, Sep 17 PM 
13:15 - 14:05
(20) 13:15-13:40 Quantitative Performance Evaluation of Arbiter PUFs on FPGAs RECONF2010-37 Yohei Hori (AIST), Takahiro Yoshida (Chuo Univ.), Toshihiro Katashita, Akashi Satoh (AIST)
(21) 13:40-14:05 Implementation and Evaluation of ScalableCore System 2.0 RECONF2010-38 Yoshito Sakaguchi, Shinya Takamaeda, Kenji Kise (Tokyo Tech)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address Nobuya WATANABE (Okayama Univ.)
E-: bu-u
TEL: +81-86-251-8251
FAX: +81-86-251-8251 

Last modified: 2010-09-06 21:40:28

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