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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Yuichiro Shibata (Nagasaki Univ.) Vice Chair: Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary: Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)
Assistant: Hiroki Nakahara (Tokyo Inst. of Tech.), Yukitaka Takemura (INTEL)

DATE:
Thu, Sep 10, 2020 13:30 - 16:55
Fri, Sep 11, 2020 10:00 - 16:25

PLACE:
Online(Takefumi Miyoshi, e-trees.Japan/WasaLabo)

TOPICS:
Reconfigurable system, etc.

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Thu, Sep 10 PM (13:30 - 14:45)
Chair: Takefumi Miyoshi
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(1) 13:30 - 13:55
With GPU-FPGA Heterogeneous computing, Highly Effective Communication for Distributed Deep Learning
Kenji Tanaka, Yuki Arikawa, Tsuyoshi Ito, Kazutaka Morita, Naru Nemoto, Fumiaki Miura, Kazuhiko Terada, Junji Teramoto, Takashi Sakamoto (NTT)

(2) 13:55 - 14:20
(See Japanese page.)

(3) 14:20 - 14:45
Development of Multi-tenant Resource Management for Multi-FPGA Cloud Systems
Miho Yamakura (Keio Univ./AIST), Ryousei Takano, Akram Ben Ahmed (AIST), Hideharu Amano (Keio Univ.)

----- Break ( 15 min. ) -----

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Thu, Sep 10 PM (15:00 - 15:50)
Chair: Yoshiki Yamaguchi
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(4) 15:00 - 15:50
[Invited Talk]
Introduction of oneAPI and Current status of Intel FPGA Technolgies
Yukitake Takemura (Intel)

----- Break ( 15 min. ) -----

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Thu, Sep 10 PM (16:05 - 16:55)
Chair: Hideki Takase
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(5) 16:05 - 16:30
(See Japanese page.)

(6) 16:30 - 16:55
An implementation of an object detection algorhythm on Vitis AI and Winning a prize in the 2nd AI Edge
Katsunoshin Matsui, Hiromu Miyazaki, Kazuki Nakano, Kenji Kise (Tokyo Tech)

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Fri, Sep 11 AM (10:00 - 10:50)
Chair: Hiroki Nakahara
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(7) 10:00 - 10:25
(See Japanese page.)

(8) 10:25 - 10:50
(See Japanese page.)

----- Break -----

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Fri, Sep 11 PM (13:00 - 13:50)
Chair: Yuichiro Shibata
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(9) 13:00 - 13:50
[Invited Talk]
Applications and Technology Innovations for an FPGA
-- Current Technologies and its Future Prospects --
Yoshihiro Horie (Xilinx)

----- Break ( 40 min. ) -----

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Fri, Sep 11 PM (14:30 - 15:20)
Chair: Yukitake Takemura
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(10) 14:30 - 14:55
(See Japanese page.)

(11) 14:55 - 15:20
An FPGA-Based Low-Latency Accelerator for Randomly Wired Convolutional Neural Networks
Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech)

----- Break ( 15 min. ) -----

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Fri, Sep 11 PM (15:35 - 16:25)
Chair: Yuki Kobayashi
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(12) 15:35 - 16:00
Inductive Invariant Generation Based on Binary Decision Diagram and its Application to Logic Synthesis
Liu ZiHao, Miyasaka Yukio, Fujita Masahiro (UT)

(13) 16:00 - 16:25
TAI Compiler: Deep Learning Inference Optimizer for an FPGA
Hiroki Nakahara (TAI)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:

Tue, Nov 17, 2020 - Wed, Nov 18, 2020: Online [Mon, Sep 7], Topics: Design Gaia 2020 -New Field of VLSI Design-

# SECRETARY:
Yuichiro Shibata（Nagasaki Univ.）
E-mail: