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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Noriyuki Minegishi (Mitsubishi Electric) Vice Chair: Nozomu Togawa (Waseda Univ.) Secretary: Koyo Nitta (NTT), Yukihide Kohira (Univ. of Aizu) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Yutaka Tamiya (Fujitsu Lab.) Secretary: Seiya Shibata (NEC), Yukio Mitsuyama (Kochi Univ. of Tech.), Eiichi Hosoya (NTT) Assistant: Hiroe Iwasaki (NTT) DATE: Wed, May 15, 2019 13:30 - 20:00 PLACE: Tokyo Institute of Technology, Ookayama Campus(2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550 Japan. 1-minute walk from Ookayama Station. https://www.titech.ac.jp/english/maps/#ookayama) TOPICS: System Design, etc. ---------------------------------------- Wed, May 15 PM (13:30 - 14:45) ---------------------------------------- (1) 13:30 - 13:55 (2)/VLD 13:55 - 14:20 A study on replica topology and temperature assignment for Ising-Model based Solver via Parallel Tempering Akira Dan, Takashi Sato (Kyoto Univ.) (3)/VLD 14:20 - 14:45 Approximate Computing Technique Using Memoization and Simplified Multiplication Yoshinori Ono, Kimiyoshi Usami (SIT) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, May 15 PM (15:00 - 16:15) ---------------------------------------- (4)/VLD 15:00 - 15:25 Study of new stacked type logic circuit scheme with fabrication technology of 3D flash memory Fumiya Suzuki, Shigeyoshi Watanabe (Shonan Inst. of Tech.) (5)/VLD 15:25 - 15:50 SRAM-Based Synthesis for Multi-Output Gates Xingming Le, Amir Masoud Gharehbaghi, Masahiro Fujita (The Univ. of Tokyo) (6)/VLD 15:50 - 16:15 The real chip evaluation of Through Chip Interface IP for Renesas 65nm SOTB process Hideharu Amano, Hideto Kayashima, Tsunaaki Shidei, Takuya Kojima (Keio Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, May 15 PM (16:30 - 17:30) ---------------------------------------- (7)/VLD 16:30 - 17:30 [Invited Talk] Viaswitch FPGA for Energy Efficient Computing Masanori Hashimoto (Osaka Univ.) ----- Break ( 30 min. ) ----- ---------------------------------------- Wed, May 15 PM (18:00 - 20:00) ---------------------------------------- (8) 18:00 - 20:00 # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. # CONFERENCE SPONSORS: - This conference is supported by IEEE CEDA All Japan Joint Chapter. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Tue, Jul 30, 2019 - Wed, Jul 31, 2019: Iwate Univ. [Thu, May 16] # SECRETARY: Koyo Nitta (NTT) E-mail:  t        # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # SECRETARY: Yukio Mitsuyama (Kochi Univ. of Tech.) E-mail:       o -  # ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ Last modified: 2019-05-15 21:16:20 |
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