===============================================
Technical Committee on VLSI Design Technologies (VLD)
Chair: Makoto Ikeda (Univ. of Tokyo) Vice Chair: Toshiyuki Shibuya (Fujitsu Labs.)
Secretary: Shigetoshi Nakatake (Univ. of Kitakyushu), Noriyuki Minegishi (Mitsubishi Electric)
===============================================
Technical Committee on Component Parts and Materials (CPM)
Chair: Yasushi Takano (Shizuoka Univ.) Vice Chair: Satoru Noge (Numazu National College of Tech.)
Secretary: Koji Enbutsu (NTT), Tomomasa Sato (Kanagawa Univ.)
Assistant: Junichi Kodate (NTT), Nobuyuki Iwata (Nihon Univ.)
===============================================
Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Takeshi Yamamura (Fujitsu Labs.) Vice Chair: Minoru Fujishima (Hiroshima Univ.)
Secretary: Toshimasa Matsuoka (Osaka Univ.), Osamu Watanabe (Toshiba)
Assistant: Shinichi Ouchi (AIST), Takeshi Yoshida (Hiroshima Univ.), Akira Tsuchiya (Kyoto Univ.), Pham Konkuha (Univ. of Electro-Comm.)
===============================================
Technical Committee on Computer Systems (CPSY)
Chair: Tsutomu Yoshinaga (Univ. of Electro-Comm.) Vice Chair: Akira Asato (Fujitsu), Yasuhiko Nakajima (NAIST)
Secretary: Koji Nakano (Hiroshima Univ.), Hidetsugu Irie (Univ. of Electro-Comm.)
Assistant: Hiroaki Inoue (NEC), Takeshi Ohkawa (Utsunomiya Univ.)
===============================================
Technical Committee on Dependable Computing (DC)
Chair: Seiji Kajihara (Kyushu Inst. of Tech.) Vice Chair: Nobuyasu Kanekawa (Hitachi)
Secretary: Tomohiro Nakamura (Hitachi), Tatsuhiro Tsuthiya (Osaka Univ.)
===============================================
Technical Committee on Reconfigurable Systems (RECONF)
Chair: Tetsuo Hironaka (Hiroshima City Univ.)
Vice Chair: Minoru Watanabe (Shizuoka Univ.), Masato Motomura (Hokkaido Univ.)
Secretary: Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba)
Assistant: Kazuya Tanikagawa (Hiroshima City Univ.)
===============================================
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Michiaki Muraoka (Kochi Univ.)
Secretary: Naoki Iwata (Sony), Kotaro Shimamura (Hitachi), Makoto Sugihara (Kyushu Univ.)
DATE:
Wed, Nov 27, 2013 08:50 - 16:50
Thu, Nov 28, 2013 08:30 - 18:00
Fri, Nov 29, 2013 08:30 - 15:00
PLACE:
(http://www.houzanhall.com/access/index.html. Prof. Hiroki Nakahara)
TOPICS:
Design Gaia 2013 -New Field of VLSI Design-
----------------------------------------
Wed, Nov 27 AM (10:00 - 11:40)
----------------------------------------
(1)/VLD 10:00 - 10:25
A VLSI algorithm for computing correctly rounded hypotenuse
Hiroyuki Yataka, Naofumi Takagi (Kyoto Univ.)
(2)/VLD 10:25 - 10:50
Fast distance calculation method for rooted tree with CUDA
Hiroki Sakamoto, Yasuhiro Takashima (Univ. of Kitakyushu)
(3)/VLD 10:50 - 11:15
Adjacent Common Centroid Placement for Analog IC Layout Design
Kenichiro Murotatsu, Kunihiro Fujiyoshi (TUAT)
(4)/VLD 11:15 - 11:40
An Optimal Sample Preparation Algorithm for Digital Microfluidic Biochips
Trung Anh Dinh, Shigeru Yamashita (Ritsumeikan University Univ.), Tsung-Yi Ho (National Cheng Kung Univ.)
----------------------------------------
Wed, Nov 27 PM (13:00 - 13:50)
----------------------------------------
(5) 13:00 - 13:50
[Invited Talk]
Minimal fab
-- One by one manufacturing of devices --
Shiro Hara, Hitoshi Maekawa, Shinichi Ikeda, Shizuka Nakano, Sommawan Khumpuang (AIST)
----- Break ( 15 min. ) -----
----------------------------------------
Wed, Nov 27 PM (14:05 - 15:45)
----------------------------------------
(6)/VLD 14:05 - 14:30
A Heuristic Design Method for Yield Improvement based on PPCs
Shunichi Sanae, Yuko Hara-Azumi (NAIST), Shigeru Yamashita (Ritsumeikan Univ.), Yasuhiko Nakashima (NAIST)
(7)/VLD 14:30 - 14:55
Fault-Tolerant Design with Less Overhead than DMR
Atsushi Matsuo, Shigeru Yamashita (Ritsumeikan Univ.)
(8)/VLD 14:55 - 15:20
Suspicious timing error prediction using check points
Hiroaki Igarashi, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(9)/DC 15:20 - 15:45
A controller design in high-level synthesis for multi-cycle transient fault tolerance
Yutaro Ishimori, Tatsuya Nakaso, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
----------------------------------------
Wed, Nov 27 AM (10:00 - 11:40)
----------------------------------------
(10) 10:00 - 10:25
(11) 10:25 - 10:50
(12)/VLD 10:50 - 11:15
A Hardware/Software Simulator for NoC using SystemC and QEMU
Yosuke Kurimoto, Yusuke Fukutsuka, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)
(13) 11:15 - 11:40
----------------------------------------
Wed, Nov 27 PM (13:00 - 13:50)
----------------------------------------
(14)/RECONF 13:00 - 13:25
A High-Speed FFT for a Solar Radio Burst Obvervation on a Radio Telescope
Hiroki Nakahara, Youhei Chishiki (Kagoshima Univ.), Kazumasa Iwai (NAOJ), Hiroyuki Nakanishi (Kagoshima Univ.)
(15)/RECONF 13:25 - 13:50
An Update Method for a CAM Emulator using a LUT Cascade Based on an EVBDD
Kensuke Kushiyama, Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.)
----- Break ( 15 min. ) -----
----------------------------------------
Wed, Nov 27 PM (14:05 - 15:20)
----------------------------------------
(16)/VLD 14:05 - 14:30
Improved via programmable structured ASIC VPEX3S
-- Improvement of basic logic element to improve operation speed --
Taku Otani, Ryohei Hori (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
(17)/VLD 14:30 - 14:55
New Via Programmable Architecture VPEX4 (1)
-- Development of new logic element for improvement of routability and power consumption --
Ryohei Hori, Taku Otani, Tatsuro Hitomi, Shota Ueguchi (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
(18)/VLD 14:55 - 15:20
Evaluation of Via Programmable Device named VPEX using benchmark circuits
Shota Ueguchi, Ryohei Hori, Taku Otani (Ritsumeikan Univ.), Masaya Yoshikawa (Meijyo Univ.), Takeshi Fujino (Ritsumeikan Univ.)
----------------------------------------
Wed, Nov 27 AM (08:50 - 10:05)
----------------------------------------
(19)/ICD 08:50 - 09:15
Automatic distortion compensation technique in resistor ladder for high-speed and low-power ADC
Wataru Yoshimura, Kenichi Ohhata (Kagoshima Univ.)
(20)/ICD 09:15 - 09:40
Co-design for reducing power supply noises with On-die PDN Impedance
Ryota Kobayashi, Hiroki Otsuka, Genki Kubo, Sho Kiyoshige, Wataru Ichimura, Masahiro Terasaki, Toshio Sudo (Shibaura Inst. of Tech.)
(21)/ICD 09:40 - 10:05
The design of Via Programmable Analog(VPA) circuit and its performance evaluation compared to programmable analog circuit
Keisuke Ueda, Ryohei Hori, Mitsuru Shiozaki, Toshio Kumamoto, Tomohiro Fujita, Takeshi Fujino (Ritsumeikan Univ.)
----- Break ( 15 min. ) -----
----------------------------------------
Wed, Nov 27 AM (10:20 - 12:00)
----------------------------------------
(22)/ICD 10:20 - 10:45
Performance Evaluation of Tamper-Resistant AES Cryptographic Circuit utilizing Hybrid Masking Dual-Rail ROM
Shintaro Ukai, Tsunato Nakai, Toshiki Kitamura, Takaya Kubota, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.)
(23)/ICD 10:45 - 11:10
Design and study of PUF Circuit using IO-Masked Dual-Rail ROM with Resistance against Side-Channel Attacks
Takashi Nishimura, Syuuhei Sugaya, Akihiro Takeuchi, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.)
(24)/ICD 11:10 - 11:35
A Quantizer Adaptively Predicting both Optimum Clock Frequency and Optimum Supply Voltage for Dynamic Voltage and Frequency Scaling Controlled Multimedia Processor
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)
(25)/ICD 11:35 - 12:00
Low Energy Tracking System with Dynamic Frame-Rate Optimization
Serina Egawa, Koji Inoue (Kyushu Univ.)
----------------------------------------
Wed, Nov 27 PM (13:00 - 13:50)
----------------------------------------
(26)/ICD 13:00 - 13:25
Exploring Microarchitecture for Next Generation Single-Flux-Quantum Processors
Jumpei Yokota, Tomonori Tsuhata, Koji Inoue (Kyushu Univ.), Masamitsu Tanaka (Nagoya Univ.)
(27)/ICD 13:25 - 13:50
A Method for Optimizing Power-Efficiency of an MTJ-Based Nonvolatile FPGA
Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Takahiro Hanyu (Tohoku Univ.)
----- Break ( 10 min. ) -----
----------------------------------------
Wed, Nov 27 PM (14:00 - 16:50)
----------------------------------------
(28) 14:00 - 14:40
[Invited Talk]
Circuit design for 3D-stacking using TSV interconnects
Kenichi Osada, Futoshi Furuta, Kenichi Takeda (Hitachi)
(29) 14:40 - 15:20
[Invited Talk]
3D Clock Distribution Using Vertically/Horizontally Coupled Resonators
Yasuhiro Take, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda (Keio Univ.)
----- Break ( 10 min. ) -----
(30) 15:30 - 16:10
[Invited Talk]
Cu Wiring Technology for 3D/2.5D Packaging
Motoaki Tani, Yoshihiro Nakata, Tsuyoshi Kanki, Tomoji Nakamura (Fujitsu Lab.)
(31) 16:10 - 16:50
[Invited Talk]
Chip Thinning Technologies for Chip Stacking Packages
Shinya Takyu, Tetsuya Kurosawa (Toshiba)
----------------------------------------
Thu, Nov 28 AM (08:30 - 10:10)
----------------------------------------
(32) 08:30 - 08:55
(33)/VLD 08:55 - 09:20
System-level design method considering the interrupt processing
Yuki Ando, Yukihito Ishida, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.)
(34)/VLD 09:20 - 09:45
Function-Level Profiling for Embedded Software with QEMU
Tran Van Dung, Ittetsu Taniguchi (Ritsumeikan Univ.), Takuji Hieda (Kyushu Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)
(35)/VLD 09:45 - 10:10
An Area Constraint-Based Fault-Secure HLS Algorithm for RDR Architectures Considering Trade-Off between Reliability and Time Overhead
Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
----- Break ( 15 min. ) -----
----------------------------------------
Thu, Nov 28 AM (10:25 - 12:05)
----------------------------------------
(36)/VLD 10:25 - 10:50
Development of a fine-grain power-gated CPU "Geyser-3" and adaptive power-off control to the temperature
Kimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui (Shibaura Inst. of Tech.), Weihan Wang, Hideharu Amano (Keio Univ), Ryuichi Sakamoto, Mitaro Namiki (Tokyo Univ of Agriculture and Tech), Masaaki Kondo (Univ of Elec-Comm), Hiroshi Nakamura (Univ of Tokyo)
(37)/VLD 10:50 - 11:15
Energy evaluation of writing reduction method for non-volatile memory
Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
(38)/VLD 11:15 - 11:40
Power Reduction of Non-volatile Logic Circuits Using the Minimum Writing Power Cut-set of State Registers
Yudai Itoi, Shinji Kimura (Waseda Univ.)
(39) 11:40 - 12:05
----------------------------------------
Thu, Nov 28 PM (13:20 - 14:35)
----------------------------------------
(40)/VLD 13:20 - 13:45
Evaluations of Variations on Ring Oscillators from Plasma Induced Damage in Bulk and SOTB Processes
Ryo Kishida, Michitarou Yabuuchi, Azusa Oshima, Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
(41)/DC 13:45 - 14:10
A Study on Design Structure of Ring Oscillators with Plural Frequency Characteristics in FPGAs
Yousuke Miyake, Masafumi Monden, Yasuo Sato, Seiji Kajihara (Kyusyu Inst. of Tech.)
(42)/DC 14:10 - 14:35
An inverter block construction method to reduce test data volume on BAST
Marika Tanaka, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushu Univ), Masayuki Arai (Nihon Univ), Michinobu Nakao (Yomiuri Institute)
----- Break ( 15 min. ) -----
----------------------------------------
Thu, Nov 28 PM (15:15 - 16:45)
----------------------------------------
(43) 15:15 - 16:45
----- Break ( 15 min. ) -----
----------------------------------------
Thu, Nov 28 PM (17:00 - 18:00)
----------------------------------------
(44) 17:00 - 18:00
[Keynote Address]
The age of Space Discovery Opened by World's First Solar Sail "IKAROS"
Osamu Mori (JAXA)
----------------------------------------
Thu, Nov 28 AM (08:30 - 09:45)
----------------------------------------
(45)/RECONF 08:30 - 08:55
Soft-core microprocessor for small reconfigurable device
Yuichi Watanabe, Taisuke Yamamoto, Yuki Yoshida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.)
(46)/RECONF 08:55 - 09:20
Mapping of Java bytecode to virtual CGRA with implementation in FPGA
Yuki Ogawa, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(47)/RECONF 09:20 - 09:45
A trade-off between hardware resources and detection accuracy for FPGA implementation of separability filters
Jimpei Hamamura, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
----- Break ( 15 min. ) -----
----------------------------------------
Thu, Nov 28 AM (10:00 - 10:50)
----------------------------------------
(48)/RECONF 10:00 - 10:25
ILP-Based Placement and Routing Method for PLDs for Minimizing Critical Path Length
Hiroki Nishiyama, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
(49)/RECONF 10:25 - 10:50
Automatic synthesis of the inter-processor communication implimentation for hetero multiprocessor systems
Yukihito Ishida, Yuki Ando, Shinya Honda, Hiroaki Takada, Masato Edahiro (Nagoya Univ.)
----- Break ( 15 min. ) -----
----------------------------------------
Thu, Nov 28 AM (11:05 - 11:55)
----------------------------------------
(50) 11:05 - 11:55
[Invited Talk]
Toward VLSI Reliability Enhancement by Reconfigurable Architecture
Takao Onoye, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Dawood Alnajjar, Hiroaki Konoura (Osaka Univ.)
----------------------------------------
Thu, Nov 28 PM (13:20 - 15:00)
----------------------------------------
(51)/RECONF 13:20 - 13:45
Real Chip evaluation of a low power reconfigurable accelerator with SOTB Technology
Hongliang Su, Hideharu Amano (Keio Univ.)
(52)/RECONF 13:45 - 14:10
Evaluation of The First Flex Power FPGA chip with SOTB transistors
Chao Ma (AIST/Meiji Univ.), Masakazu Hioki (AIST), Takashi Kawanami (KIT), Yasuhiro Ogasahara, Tadashi Nakagawa, Toshihiro Sekigawa (AIST), Toshiyuki Tsutsumi (AIST/Meiji Univ.), Hanpei Koike (AIST)
(53)/RECONF 14:10 - 14:35
Dependability-increasing demonstration of an optically differential reconfigurable gate array
Masato Seo, Minoru Watanabe (Shizuoka Univ.)
(54)/RECONF 14:35 - 15:00
Architecture Evaluation Using The Place-and-Route Tool of a Reconstruction Device MPLD
Tomoya Yamashita, Masato Inagi, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (TAIYO YUDEN)
----- Break ( 15 min. ) -----
----------------------------------------
Thu, Nov 28 AM (09:00 - 10:15)
----------------------------------------
(55) 09:00 - 09:25
(56) 09:25 - 09:50
(57) 09:50 - 10:15
----- Break ( 15 min. ) -----
----------------------------------------
Thu, Nov 28 AM (10:30 - 11:45)
----------------------------------------
(58)/VLD 10:30 - 10:55
On Synthesis Algorithm for Parallel Index Generator Units
Yusuke Matsunaga (Kyushu Univ.)
(59)/VLD 10:55 - 11:20
A thermal analysis algorithm for VLSI chip by GPGPU
Takashi Ohmura, Lei Lin, Lin Meng, Masahiro Fukui (Ritsumeikan Univ.)
(60)/VLD 11:20 - 11:45
List Scheduling Algorithms for Task Graphs with Data Parallelism
Yang Liu, Ittetsu Taniguchi, Hiroyuki Tomiyama, Lin Meng (Ritsumeikan Univ.)
----------------------------------------
Thu, Nov 28 PM (13:20 - 14:35)
----------------------------------------
(61)/CPSY 13:20 - 13:45
Study of the Hardware Trojan for Embedded Processor
Yasushi Tsukada, Shuhei Itaya, Takeshi Kumaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijou Univ), Takeshi Fujino (Ritsumeikan Univ.)
(62)/CPSY 13:45 - 14:10
Implementation of a fast runtime visualization of a GPU-based electromagnetic simulation using a 3D-FDTD method
Kota Aoki, Keisuke Dohi, Yuichiro Shibata, Kiyoshi Oguri, Takafumi Fujimoto (Nagasaki Univ.)
(63)/CPSY 14:10 - 14:35
TinyCSE: Tiny Computer System for Education
Ryosuke Nakamura, Koji Nakano, Yasuaki Ito (Hiroshima Univ.)
----- Break ( 40 min. ) -----
----------------------------------------
Fri, Nov 29 AM (08:30 - 10:10)
----------------------------------------
(64)/DC 08:30 - 08:55
A Study of Burn-In Test Prediction by Data Mining
Satoshi Nonoyama, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.), Yoshiyuki Nakamura (Renesas Electronics)
(65)/DC 08:55 - 09:20
A Method of LFSR Seed Generation for Delay Fault BIST
Taro Honda, Satoshi Ohtake (Oita Univ.)
(66)/DC 09:20 - 09:45
Design and evaluation of circuits to control scan-in power in logic BIST
Takaaki Kato, Takeru Kina, Yousuke Miyake, Yasuo Sato, Seiji Kajihara (Kyushu Inst. of Tech.)
(67)/DC 09:45 - 10:10
A Method of High Quality Transition Test Generation Using RTL Information
Hiroyuki Nakashima, Satoshi Ohtake (Oita Univ.)
----- Break ( 15 min. ) -----
----------------------------------------
Fri, Nov 29 AM (10:25 - 12:05)
----------------------------------------
(68)/VLD 10:25 - 10:50
Forwarding Unit Generation for Loop Pipelining in High-Level Synthesis
Shingo Kusakabe, Tomohito Toyama, Kenshu Seto (Tokyo City Univ.)
(69) 10:50 - 11:15
(70)/VLD 11:15 - 11:40
Estimation for Method of Controller Implementation in High-Level Synthesis
Ryoya Sobue (Ritsumeikan Univ.), Yuko Hara-Azumi (NAIST), Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)
(71)/VLD 11:40 - 12:05
Clock Energy-efficient High-level Synthesis and Experimental Evaluation for HDR-mcd Architecture
Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech./Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
----------------------------------------
Fri, Nov 29 PM (13:20 - 15:00)
----------------------------------------
(72)/VLD 13:20 - 13:45
Scheduling of PDE Setting and Timing Test for Post Silicon Skew Tuning
Mineo Kaneko (JAIST)
(73)/VLD 13:45 - 14:10
A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delay Values for Yield Improvement
Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)
(74)/VLD 14:10 - 14:35
A Method and Evaluation of Dynamic Relocation for Shared Multi-FPGA System
Yuta Ukon, Takuya Otsuka, Takashi Aoki, Yusuke Sekihara, Akihiko Miyazaki (NTT)
(75)/VLD 14:35 - 15:00
A Study on the Design of Processor System for Stream Processing
Yusuke Sekihara, Koji Yamazaki, Akihiko Miyazaki (NTT)
----------------------------------------
Fri, Nov 29 AM (09:00 - 09:50)
----------------------------------------
(76) 09:00 - 09:50
[Invited Talk]
What is happening in Silicon Valley.
-- Wearable, Mobile, Big Data, and Ecosystem --
Yasunori Kimura (FLA)
----- Break ( 15 min. ) -----
----------------------------------------
Fri, Nov 29 AM (10:05 - 11:45)
----------------------------------------
(77)/CPSY 10:05 - 10:30
A Study on an optimal architecture for stream mining applications with FPGA
Sayaka Akioka (Meiji Univ.)
(78)/CPSY 10:30 - 10:55
A circuit division method for High-Level synthesis on Multi-FPGA systems in stream processing
Daiki Kugami, Takaaki Miyajima, Hideharu Amano (Keio Univ.)
(79)/CPSY 10:55 - 11:20
A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs
Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, Yasuaki Ito (Hiroshima Univ.)
(80)/CPSY 11:20 - 11:45
A study of multi-port shared cache architecture for a multi-core processor on an FPGA
Hongkun Jin, Yoshiki Yamaguchi, Yuetsu Kodama (Univ. of Tsukuba)
----------------------------------------
Fri, Nov 29 PM (13:20 - 14:10)
----------------------------------------
(81)/CPSY 13:20 - 13:45
NoC routers using the marching memory through type
Ryota Yasudo, Takahiro Kagami, Hideharu Amano (Keio Univ.), Yasunobu Nakase, Masashi Watanabe, Tsukasa Oishi, Toru Shimizu (Renesas), Tadao Nakamura (Keio Univ.)
(82)/CPSY 13:45 - 14:10
A 3-D NoC architecture using CSMA/CD bus for inter-chip wireless communication
Takahiro Kagami, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:
Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Hiyoshi Campus, Keio University [Fri, Nov 15], Topics: FPGA Applications, etc
# ANNOUNCEMENT:
# See also VLD's homepage:
http://www.ieice.org/~vld/
=== Technical Committee on Component Parts and Materials (CPM) ===
# FUTURE SCHEDULE:
Thu, Nov 28, 2013 - Fri, Nov 29, 2013: [Wed, Sep 18], Topics: Ｎｉｔｒide and Compound Semiconductor Devices
Thu, Feb 27, 2014: Kikai-Shinko-Kaikan Bldg. [Sun, Dec 8]
=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:
Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Kyoto Univ. Tokeidai Kinenkan [Fri, Nov 22]
=== Technical Committee on Computer Systems (CPSY) ===
# FUTURE SCHEDULE:
Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Hiyoshi Campus, Keio University [Fri, Nov 15], Topics: FPGA Applications, etc
=== Technical Committee on Dependable Computing (DC) ===
# FUTURE SCHEDULE:
Fri, Dec 13, 2013: [Mon, Oct 14], Topics: Safety, etc.
Mon, Feb 10, 2014: Kikai-Shinko-Kaikan Bldg. [Thu, Dec 12], Topics: VLSI Design and Test, etc.
=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:
Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Hiyoshi Campus, Keio University [Fri, Nov 15], Topics: FPGA Applications, etc
=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
# FUTURE SCHEDULE:
Tue, Jan 28, 2014 - Wed, Jan 29, 2014: Hiyoshi Campus, Keio University [Fri, Nov 15], Topics: FPGA Applications, etc
# ANNOUNCEMENT:
# Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/
Last modified: 2013-11-12 18:21:41
|
Notification: Mail addresses are partially hidden against SPAM.
|