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Technical Committee on Hardware Security (HWS)
Chair: Tsutomu Matsumoto (Yokohama National Univ.) Vice Chair: Shinichi Kawamura (Toshiba), Makoto Ikeda (Univ. of Tokyo)
Secretary: Noriyuki Miura (Kobe Univ.), Hiroki Kunii (SECOM)

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Technical Committee on VLSI Design Technologies (VLD)
Chair: Noriyuki Minegishi (Mitsubishi Electric) Vice Chair: Nozomu Togawa (Waseda Univ.)
Secretary: Koyo Nitta (NTT), Yukihide Kohira (Univ. of Aizu)

DATE:
Wed, Feb 27, 2019 10:25 - 17:35
Thu, Feb 28, 2019 10:00 - 17:35
Fri, Mar 1, 2019 10:00 - 17:35
Sat, Mar 2, 2019 10:00 - 14:45

PLACE:
Okinawa Ken Seinen Kaikan(http://www.okiseikan.or.jp/)

TOPICS:
Design Technology for System-on-Silicon, Hardware Security, etc.

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Wed, Feb 27 AM VLD(1) (10:25 - 11:40)
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(1) 10:25 - 10:50
FPGA Implementation of Fully Convolutional Network for Semantic Segmentation
Masayuki Shimoda, Youki Sada, Hiroki Nakahara (titech)

(2) 10:50 - 11:15
Spatial-Separable Convolution: Low memory CNN for FPGA
Akira Jinguji, Masayuki Shimoda, Hiroki Nakahara (titech)

(3) 11:15 - 11:40
A Case Study on Approximate Multipliers for MNIST CNN
Kenta Shirane, Takahiro Yamamoto (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)

----- Lunch Break ( 60 min. ) -----

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Wed, Feb 27 PM VLD(2) (12:40 - 14:20)
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(4) 12:40 - 13:05
Pattern Matching Based Detection of Wire Congestion from Source Code Description for High Level Synthesis
Masato Tatsuoka, Mineo Kaneko (JAIST)

(5) 13:05 - 13:30
Wire Load Model for Power Consumption Evaluation of Via-Switch FPGA
Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)

(6) 13:30 - 13:55
Routing Algorithm to Achieve Circular Wire for SIM-Type SADP
Shun Akatsuka, Kunihiro Fujiyoshi (TUAT)

(7) 13:55 - 14:20
Set-Pair Routing Algorithm with Selective Pin-Pair Connections
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech)

----- Break ( 10 min. ) -----

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Wed, Feb 27 PM VLD(3) (14:30 - 16:10)
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(8) 14:30 - 14:55
Function-level Module Sharing with High-level Synthesis
Ryohei Nozaki (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)

(9) 14:55 - 15:20
High-Level Synthesis of the CHStone Benchmark Programs with SDSoC
Takuya Adachi (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)

(10) 15:20 - 15:45
Design Flow of Circuits with Multiple Supply Voltages for Power Reduction in General-Synchronous Framework
Masataka Aoki, Yukihide Kohira (Univ. of Aizu)

(11) 15:45 - 16:10
Timing Correction by Constrained Temperature Dependent Clock Skew
Mineo Kaneko (JAIST)

----- Break ( 10 min. ) -----

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Wed, Feb 27 PM VLD(4) (16:20 - 17:35)
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(12) 16:20 - 16:45
A Battery Degradation aware System Level Battery Management Methodology
Daichi Watari, Ittetsu Taniguchi, Takao Onoye (Osaka Univ.)

(13) 16:45 - 17:10
Design of an FPGA-based Manycore Architecture with Selective Local/Global Memory
Seiya Shirakuni (Ritsumeikan Univ.), Ittetsu Taniguchi (Osaka Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.)

(14) 17:10 - 17:35
Improvement on DMA Transfer Efficiency by Packet Concatenation
Shoko Ohteru, Saki Hatta, Tomoaki Kawamura, Koji Yamazaki, Takahiro Hatano, Akihiko Miyazaki, Koyo Nitta (NTT)

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Thu, Feb 28 AM VLD(5) (10:00 - 11:40)
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(15) 10:00 - 10:25
Thermal transient analysis and evaluation of the heat generation and dissipation in three-dimensional stacked LSI
Ryota Horigome, Kimiyoshi Usami (Shibaura Inst. of Tech.)

(16) 10:25 - 10:50
Evaluation of low power consumption Standard Cell Memory (SCM) using body-bias control in Silicon-on-Thin-BOX MOSFET:SOTB
Ryo Magasaki, Yusuke Yoshida (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech.)

(17) 10:50 - 11:15
Single Supply Level Shifter Circuit using body-bias
Yuki Takeyoshi, Kimiyoshi Usame (SIT)

(18) 11:15 - 11:40
Implementation Technology for the Advanced Wafer Manufacturing Processes on Optical Transmission LSIs
Susumu Hirano, Hideo Yoshida, Kenya Sugihara, Yoshiaki Konishi, Takashi Sugihara, Yoshihiro Ogawa (Mitsubishi Electric)

----- Lunch Break ( 60 min. ) -----

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Thu, Feb 28 PM VLD(6) (12:40 - 14:20)
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(19) 12:40 - 13:05
*
Yuka Aizawa, Masashi Tawada (Waseda Univ.), Yuta Ideguchi, Norifumi Kamiya (NEC), Nozomu Togawa (Waseda Univ.)

(20) 13:05 - 13:30
High-Speed and Noise-Tolerant High-Radix Tree Domino Adder Targeted to 65 nm FD-SOI Technology
Kazuki Niino, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)

(21) 13:30 - 13:55
Selection of Gaussian Mixture Reduction Methods Using Machine Learning
Haruki Kazama, Shuji Tsukiyama (Chuo Univ.)

(22) 13:55 - 14:20
Model Compression for ECG Signals Outlier Detection Hardware trained by Sparse Robust Deep Autoencoder
Naoto Soga, Shimpei Sato, Hiroki Nakahara (Titech)

----- Break ( 10 min. ) -----

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Thu, Feb 28 PM VLD(7) (14:30 - 16:10)
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(23) 14:30 - 14:55
[Memorial Lecture]
Towards Practical Homomorphic Email Filtering: A Hardware-Accelerated Secure Naive Bayesian Filter
Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.)

(24) 14:55 - 15:20
[Memorial Lecture]
Methods for Reducing Power and Area of BDD-based Optical Logic Circuits
Ryosuke Matsuo, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.), Akihiko Shinya, Masaya Notomi (NTT)

(25) 15:20 - 15:45
A SPICE Model Parameter Extraction Environment Using Automatic Differentiation
Aoi Ueda (NNCT), Michihiro Shintani (NAIST), Hiroshi Iwata, Ken'ichi Yamaguchi (NNCT), Michiko Inoue (NAIST)

(26) 15:45 - 16:10
An Algorithm to Determine Circuit Model Parameters for Electric Double-Layer Capacitor
Naoki Kosaka, Shuji Tsukiyama (Chuo Univ.), Kenichi Noto, Takuji Okumura (Komatsu Ltd.)

----- Break ( 10 min. ) -----

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Thu, Feb 28 PM HWS(1) (16:20 - 17:35)
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(27) 16:20 - 16:45
Design of High-Speed Gaussian Sampler Using Micciancio-Walter Algorithm
Keitaro Koga (UTokyo), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo)

(28) 16:45 - 17:10
Fundamental Study on Individual Identification Method of Electronic Device Using Difference of Radiation Spectrum Caused by Manufacturing/Mounting Variations
Shugo Kaji (NAIST), Masahiro kinugawa (NIT), Daisuke Fujimoto (NAIST), Laurent Sauvage, Jean-Luc Danger (Telecom ParisTech), Yu-ichi Hayashi (NAIST)

(29) 17:10 - 17:35
Error correction method for PUF utilizing the Pixel Variation in the CMOS Image Sensor
Ryota Ishiki, Masayoshi Shirahata (Ritsumeikan Univ.), Shunsuke Okura (Brillnics), Mitsuru Shiozaki, Takaya Kubota (Ritsumeikan Univ.), Kenichiro Ishikawa, Isao Takayanagi (Brillnics), Takeshi Fujino (Ritsumeikan Univ.)

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Fri, Mar 1 AM VLD(8) (10:00 - 11:40)
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(30) 10:00 - 10:25
Synthesis of Full Hardware Implementation of RTOS-Based Systems
Yuuki Oosako, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM)

(31) 10:25 - 10:50
A Study on Placement Constraints for Asynchronous Circuits with Bundled-data Implementation aimed for FPGAs
Tatsuki Otake, Hiroshi Saito (UoA)

(32) 10:50 - 11:15
Reinforcing Generation of Instruction Sequences in Random Testing of Android Virtual Machine
Ryotaro Shimizu, Nagisa Ishiura (Kwansei Gakuin Univ.)

(33) 11:15 - 11:40
Synthesis of Distributed Control Circuits for Dynamic Scheduling across Multiple Dataflow Graphs
Sayuri Ota, Nagisa Ishiura (Kwansei Gakuin Univ.)

----- Lunch Break ( 60 min. ) -----

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Fri, Mar 1 PM VLD(9) (12:40 - 14:20)
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(34) 12:40 - 13:05
On evaluation of an efficient SAT attack algorithm for logic encryption
Yusuke Matsunaga (Kyushu Univ.), Masayoshi Yoshimura (Kyoto Sangyou Univ.)

(35) 13:05 - 13:30
A Study on Quantized HOG Calculation suitable for Hardware Implementation
Yusuke Sekiguchi, Yoichi Tomioka, Junji Kitamichi (UoA.)

(36) 13:30 - 13:55
Energy-Efficient, Small-Scale Multicore Processor towards IoT Edge Computing
Sayuri Onagi, Kaoru Saso, Yuko Hara-Azumi (Tokyo Tech.)

(37) 13:55 - 14:20
Embedded Systems Designs Using Approximate Computing for Data Clustering Acceleartion
Shun Kimijima, Fransiscus Marcel Satria, Yuko Hara-Azumi (Tokyo Tech.)

----- Break ( 10 min. ) -----

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Fri, Mar 1 PM HWS(2) (14:30 - 16:10)
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(38) 14:30 - 14:55
Integrated Circuit Design and Evaluation of Chip-Package-Board Interactive PUF Based on Wireless Chaos Oscillation
Masanori Takahashi, Makoto Nagata, Noriyuki Miura (Kobe Univ.)

(39) 14:55 - 15:20
Performance and Security Evaluation of Ring Oscillator PUF Implemented on ASIC
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)

(40) 15:20 - 15:45
An Attack with Linear Model Against Improved Arbiter PUF
Susumu Matsumi, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)

(41) 15:45 - 16:10
On Machine Learning Attack Tolerance for PUF-based Device Authentication System
Tomoki Iizuka (UTokyo), Yasuhiro Ogasahara, Toshihiro Katashita, Yohei Hori (AIST), Hiromitsu Awano (Osaka Univ.), Makoto Ikeda (UTokyo)

----- Break ( 10 min. ) -----

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Fri, Mar 1 PM HWS(3) (16:20 - 17:35)
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(42) 16:20 - 16:45
Low-Cost Power Analysis Countermeasures for Unrolled Architecture Implementation PRINCE
Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)

(43) 16:45 - 17:10
A Counter Synchronization Method for MAC generation in CAN Communication
Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.)

(44) 17:10 - 17:35
An Extended of Secure Remote Management Architecture for IoT-device
Masahiro Shiraishi, Hiroki Ito, Keiichi Okabe (NTT)

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Sat, Mar 2 AM HWS(4) (10:00 - 11:15)
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(45) 10:00 - 10:25
An ultra-light weight implementation of PRINCE-family cryptographic processor
Kohei Matsuda, Makoto Nagata, Noriyuki Miura (Kobe Univ.)

(46) 10:25 - 10:50
ASIC Chip Implementation and Evaluation of Elliptic Curve Digital Signature Algorithm
Sosuke Sato, Hiroki Yoshida, Kazuki Monta (Kobe Univ.), Takaaki Okidono (ECSEC), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)

(47) 10:50 - 11:15
A Report on Adoption Rates of Android Devices Implemented Hardware-backed Key Management
Kohei Isobe, Takahito Sakamoto (SECOM)

----- Lunch Break ( 110 min. ) -----

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Sat, Mar 2 PM HWS(5) (13:05 - 14:45)
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(48) 13:05 - 13:30
A study of interference method using flicker noise for a pedestrian detection system
Hirotaka Sakakibara, Kota Yoshida, Masayoshi Shirahata, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ)

(49) 13:30 - 13:55
An Instrumentation Security Metric for ToF Depth-Image Cameras
Satoru Sakurazawa, Daisuke Fujimoto, Tsutomu Matsumoto (YNU)

(50) 13:55 - 14:20
A Study of Collision Attacks on Moving Vehicle Equipped with Stereo Vision Camera
Hiroki Nohira, Yasushi Iwata, Naoki Yoshida, Tsutomu Matsumoto (YNU)

(51) 14:20 - 14:45
Conditions for Successful Attacks on Ultrasonic Range Finder to Output Incorrect Values
Yuya Inoue, Hiroki Nohira, Naoki Yoshida, Daisuke Fujimoto, Tsutomu Matumoto (YNU)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

# CONFERENCE SPONSORS:
- This conference is supported by IEEE CEDA All Japan Joint Chapter.

=== Technical Committee on Hardware Security (HWS) ===
# FUTURE SCHEDULE:

Fri, Apr 12, 2019: Tohoku University [Mon, Feb 18], Topics: Hardware Security, etc.
Mon, May 13, 2019 - Tue, May 14, 2019: Institute of Industrial Science, University of Tokyo , Topics: LSI and System Workshop 2019

# SECRETARY:
Noriyuki Miura(Kobe University), Hiroki Kunii(SECOM)
E-mail:hws-

=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Mon, May 13, 2019 - Tue, May 14, 2019: Institute of Industrial Science, University of Tokyo , Topics: LSI and System Workshop 2019
Wed, May 15, 2019: Ookayama Campus, Tokyo Institute of Technology [Thu, Mar 14], Topics: System Design, etc.

# SECRETARY:
Koyo Nitta (NTT)
E-mail: