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Technical Committee on Silicon Device and Materials (SDM)
Chair: Tanemasa Asano Vice Chair: Toshihiro Sugii
Secretary: Shigeru Kawanaka, Hisahiro Anzai
Assistant: Syunichiro Ohmi

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Technical Committee on Integrated Circuits and Devices (ICD)
Chair: Akira Matsuzawa Vice Chair: Kunio Uchiyama
Secretary: Yoshiharu Aimoto, Makoto Nagata
Assistant: Minoru Fujishima, Yoshio Hirose

DATE:
Thu, Aug 23, 2007 08:30 - 18:00
Fri, Aug 24, 2007 08:30 - 16:55

PLACE:
Kitami Institute of Technology(165, Koen-chou, Kitami, Hokkaido, 090-8507, Japan. http://www.kitami-it.ac.jp/eng/for/about/location.htm. Prof. Masakiyo Suzuki. 0157-26-9117)

TOPICS:
VLSI Circuit and Device Technologies (High Speed, Low Voltage, and Low Power Consumption)

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Thu, Aug 23 AM (08:30 - 10:10)
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(1) 08:30 - 08:55
Development of a Multi-Core SoC with 9 CPUs and 2 Matrix Processors
Masami Nakajima, Koichi Ishimi, Hayato Fujiwara, Kazuya Ishida, Naoto Okumura, Norio Masui, Hiroyuki Kondo (Renesas)

(2) 08:55 - 09:20
Homogenous Dual-Processor core with Shared L1 Cache for Mobile Multimedia SoC
Tetsu Hosoki, Takao Yamamoto, Masayuki Yamasaki, Keisuke Kaneko, Masaitsu Nakajima (Matsushita Electric Industrial Co., Ltd.)

(3) 09:20 - 09:45
Evaluation of Heterogeneous Multicore Architecture with AAC-LC Stereo Encoding
Hiroaki Shikano (Hitachi/./Waseda Univ.), Masaki Ito, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Masafumi Onouchi, Kunio Uchiyama (Hitachi), Toshihiko Odaka (Hitachi/./Waseda Univ.), Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta (Renesas Technology), Yasutaka Wada, Keiji Kimura, Hironori Kasahara (Waseda Univ.)

(4) 09:45 - 10:10
Fast Motion Estimation Algorithm and a Low Power Motion Estimation Processor Implementing Dynamic Voltage and Frequency Scaling
Nobuaki Kobayashi, Tadayoshi Enomoto (Chuo Univ.)

----- Break ( 10 min. ) -----

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Thu, Aug 23 AM (10:20 - 12:00)
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(5) 10:20 - 11:10
[Special Invited Talk]
Design Trends of High Performance PLLs and DLLs
Shiro Dosho (Matsushita)

(6) 11:10 - 11:35
Multiphase-Output Level Shift System used in Multiphase PLL for Low Power Application
Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho (Matsushita)

(7) 11:35 - 12:00
A Periodically All-in-Phase Clocking Architecture for Multi-Core SOC Platforms
Atsufumi Shibayama, Koichi Nose, Sunao Torii, Masayuki Mizuno, Masato Edahiro (NEC)

----- Lunch Break ( 50 min. ) -----

----------------------------------------
Thu, Aug 23 PM (12:50 - 14:30)
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(8) 12:50 - 13:40
[Special Invited Talk]
Past and Future of Dynamic Voltage Scaling
Hiroyuki Mizuno (Hitachi)

(9) 13:40 - 14:05
Energy comparison between various supply voltage scheme for System LSI
Satoshi Hanami, Shigeyoshi Watanabe, Manabu Kobayashi, Toshinori Takabatake (SIT)

(10) 14:05 - 14:30
Design of high-speed low-power dual-supply-voltage sysytem LSI taking into account of gate/sub-threshold leakage current
Shigeyoshi Watanabe, Satoshi Hanami, Manabu Kobayashi, Toshinori Takabatake (SIT)

----- Break ( 5 min. ) -----

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Thu, Aug 23 PM (14:35 - 15:50)
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(11) 14:35 - 15:00
An Optimal Supply Voltage Determiner Circuit for Minimum Energy Operations
Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara (NEC Corp.)

(12) 15:00 - 15:25
Power Measurement for a Multiplier with Run Time Power Gating
Toshihiro Kashima, Seidai Takeda, Toshiaki Shirai, Naoaki Ohkubo, Kimiyoshi Usami (S.I.T)

(13) 15:25 - 15:50
A 1.92us-wake-up time thick-gate-oxide power switch technique for ultra low-power single-chip mobile processors
Kazuki Fukuoka, Osamu Ozawa, Ryo Mori, Yasuto Igarashi, Toshio Sasaki, Takashi Kuraishi, Yoshihiko Yasu, Koichiro Ishibashi (Renesas Technology)

----- Break ( 10 min. ) -----

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Thu, Aug 23 PM (16:00 - 18:00)
----------------------------------------

(14) 16:00 - 18:00
[Panel Discussion]
Dynamic Voltage & Frequency Scaling ; A Key Technology for Deep Sub-100nm SoCs !
Tadayoshi Enomoto (Chuo Univ.), Naohiko Irie (Hitachi), Hiroshi Okano (Fujitsu), Shiro Sakiyama (Matsushita), Masakatsu Nakai (Sony), Koji Nii (Renesas Technology), Masahiro Nomura (NEC), Hiroyuki Mizuno (Hitachi)

----------------------------------------
Fri, Aug 24 AM (08:30 - 10:10)
----------------------------------------

(1) 08:30 - 08:55
A Very Wideband Fully Balanced Active RC Polyphase Filter Based on CMOS Inverters in 0.18μm CMOS Technology
Keishi Komoriyama, Eiich Yoshida, Makoto Yashiki, Hiroshi Tanimoto (Kitami Inst. Tech.)

(2) 08:55 - 09:20
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variation in SoCs
Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura (Kobe Univ.), Rei Akiyama (Renesas Design), Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata (Renesas Technology), Makoto Nagata (Kobe Univ.)

(3) 09:20 - 09:45
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise
Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo)

(4) 09:45 - 10:10
A Microwave-Powered CMOS Power Supply Circuit for Integrated Si-MEMS Microsensors
Daiki Endo (TUT), Hidekuni Takao (TUT/JST-CREST), Syunsuke Kizuna (TUT), Kazuaki Sawada, Makoto Ishida (TUT/JST-CREST)

----- Break ( 10 min. ) -----

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Fri, Aug 24 AM (10:20 - 12:00)
----------------------------------------

(5) 10:20 - 11:10
[Special Invited Talk]
Effect of metal-gate/high-k on characteristics of MOSFETs for 32nm CMOS and beyond
Masato Koyama, Masahiro Koike, Yuuichi Kamimuta, Masamichi Suzuki, Kosuke Tatsumura, Yoshinori Tsuchiya, Reika Ichihara, Masakazu Goto, Koji Nagatomo, Atsushi Azuma, Shigeru Kawanaka, Kazuaki Nakajima, Katsuyuki Sekine (Toshiba Corp.)

(6) 11:10 - 11:35
Experimental Study on Mobility Universality in (100) Ultra Thin Body nMOSFET with SOI thickness of 5 nm
Ken Shimizu, Toshiro Hiramoto (Univ. of Tokyo)

(7) 11:35 - 12:00
An analysis of asymmetry and orientation dependence of n-MOSFETs
Toshihiro Matsuda, Yuya Sugiyama, Hideyuki Iwata (Toyama Pref. Univ.), Takashi Ohzone (Okayama Pref. Univ.)

----- Lunch Break ( 60 min. ) -----

----------------------------------------
Fri, Aug 24 PM (13:00 - 14:40)
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(8) 13:00 - 13:50
[Special Invited Talk]
Towards Great Nanoelectronics Country, Japan
Hisatsune Watanabe (Selete)

(9) 13:50 - 14:15
Design of High Density LSI with Three-Dimensional Transistor FinFET
-- Effect of Pattern Area Reduction with CMOS Cell Library --
Keisuke Okamoto, Keisuke Koizumi, Yu Hiroshima, Shigeyoshi Watanabe (SIT)

(10) 14:15 - 14:40
Design Method of system LSI with FinFET type DTMOS
Yu Hiroshima, Shigeyoshi Watanabe, Keisuke Okamoto, Keisuke Koizumi (SIT)

----- Break ( 10 min. ) -----

----------------------------------------
Fri, Aug 24 PM (14:50 - 16:55)
----------------------------------------

(11) 14:50 - 15:15
0.7 V SRAM Technology with Stress-Enhanced Dopant Segregated Schottky (DSS) Source/Drain Transistors for 32 nm Node
Hiroyuki Onoda, Katsura Miyashita, Takeo Nakayama, Tomoko Kinoshita, Hisashi Nishimura, Atsushi Azuma, Seiji Yamada, Fumitomo Matsuoka (Toshiba)

(12) 15:15 - 15:40
SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for suppressing read disturbance and write-current dispersion
Katsuya Miura, Takayuki Kawahara, Riichiro Takemura (Hitachi, Ltd.), Jun Hayakawa (Hitachi, Ltd./Tohoku Univ.), Michihiko Yamanouchi (Hitachi, Ltd.), Shoji Ikeda, Ryutaro Sasaki (Tohoku Univ.), Kenchi Ito, Hiromasa Takahashi, Hideyuki Matsuoka (Hitachi, Ltd.), Hideo Ohno (Tohoku Univ.)

(13) 15:40 - 16:05
An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment
Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi (Kobe Univ.), Koji Nii (Kobe Univ./Renesas Technology), Hiroshi Kawaguchi, Masahiko Yoshimoto (Kobe Univ.)

(14) 16:05 - 16:30
A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous R/W access issues
Satoshi Ishikura, M. Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi (Matushita Electric Industrial), Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara (Renesas Technology), Hironori Akamatsu (Matushita Electric Industrial)

(15) 16:30 - 16:55
A 128-Kbit, 16-Port SRAM Design with Multi-Stage-Sensing Scheme in 90-nm CMOS Technology
Koh Johguchi, Yuya Mukuda, Shinya Izumi, Hans Juergen Mattausch, Tetsushi Koide (Hiroshima Univ.)



=== Technical Committee on Silicon Device and Materials (SDM) ===
# FUTURE SCHEDULE:

Thu, Oct 4, 2007 - Fri, Oct 5, 2007: Tohoku Univ. [Fri, Aug 3], Topics: Process Science and Novel Process Technologies
Tue, Oct 30, 2007 - Wed, Oct 31, 2007: Kikai-Shinko-Kaikan Bldg. [Fri, Aug 10], Topics: Process, Device, Circuit Simulation, etc.
Fri, Nov 16, 2007: [Thu, Sep 20]

# SECRETARY:
Shigeru Kawanaka (Semiconductor Company, Toshiba)
TEL 045-770-3642, FAX 045-776-4104
E-mail:shigeru.kawanaka@toshiba.co.jp

=== Technical Committee on Integrated Circuits and Devices (ICD) ===
# FUTURE SCHEDULE:

Thu, Oct 25, 2007 - Fri, Oct 26, 2007: Aidu-Higasiyama-Onsen Kuturogijuku [Fri, Aug 17]
Mon, Nov 19, 2007 - Wed, Nov 21, 2007: Kitakyushu International Conference Center [unfixed]

# SECRETARY:
Yoshiharu Aimoto (NEC Electronics Corporation)
TEL +81-44-435-1258, +81-44-435-1878
E-mail:yoshiharu.aimoto@necel.com


Last modified: 2007-07-04 16:49:57


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