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=============================================== Technical Committee on Computer Systems (CPSY) Chair: Hideharu Amano (Keio Univ.) Vice Chair: Akira Asato (Fujitsu), Tsutomu Yoshinaga (Univ. of Electro-Comm.) Secretary: Hidetsugu Irie (Univ. of Electro-Comm.), Koji Nakano (Hiroshima Univ.) Assistant: Hiroaki Inoue (NEC) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Kimiyoshi Usami (Shibaura Inst. of Tech.) Vice Chair: Akihisa Yamada (Sharp) Secretary: Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Takashi Takenaka (NEC) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Moritoshi Yasunaga (Univ. of Tsukuba) Vice Chair: Shorin Kyo (Renesas), Tetsuo Hironaka (Hiroshima City Univ.) Secretary: Yohei Hori (AIST), Nobuya Watanabe (Okayama Univ.) Assistant: Yoshiki Yamaguchi (Univ. of Tsukuba) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Kazutoshi Wakabayashi (NEC) Secretary: Naohito Kojima (Toshiba), Hiroaki Komatsu (Fujitsu), Nozomu Togawa (Waseda Univ.) DATE: Wed, Jan 25, 2012 10:00 - 18:00 Thu, Jan 26, 2012 09:00 - 17:05 PLACE: Hiyoshi Campus, Keio University(4-1-1, Hiyoshi, Kohoku-ku, Yokohama, 223-8521, Japan. http://www.keio.ac.jp/ja/access/hiyoshi.html. Prof. Hideharu Hamano. 045-560-1064) TOPICS: FPGA Applications, etc ---------------------------------------- Wed, Jan 25 AM FPGA Applications (10:00 - 12:05) Chair: Atsushi Takahashi (Osaka Univ.) ---------------------------------------- (1)/VLD 10:00 - 10:25 Hardware TCP/IP Stack FPGA IP Core for Accelerating WEB Applications Kotoko Fujita, Nadav Bergstein, Hakaru Tamukoh, Masatoshi Sekine (TUAT) (2)/VLD 10:25 - 10:50 Detemination of Vocal Tract Shape on Voice Synthesis Circuit using Shift Register Keita Manabe, Rika Uegaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) (3)/VLD 10:50 - 11:15 Sound preprocessing circuit by consonant and vowel recognition system Keita Okamoto, Hakaru Tamukoh, Masatoshi Sekine (TUAT) (4)/VLD 11:15 - 11:40 Two Dimensional Array Processor for Moving Object Tracking using Synchronous Data Shift Takatosi Uchizono, Kazuya Osaku, Akinobu Tsuyuki, Zhu Li, Yoichi Tomioka, Hitoshi Kitazawa (TUAT) (5)/VLD 11:40 - 12:05 An Image Recognition System with Hierarchical Feature Learning Function Masahiro Ariizumi, Baku Ogasawara, Hakaru Tamukoh, Masatoshi Sekine (TUAT) ---------------------------------------- Wed, Jan 25 PM Reconfigurable and Real time Processing (13:30 - 14:45) Chair: Takeshi Takenaka (NEC) ---------------------------------------- (6)/RECONF 13:30 - 13:55 On a Decomposed MTMDDs for CF Machine Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao, Munehiro Matsuura (KIT) (7)/CPSY 13:55 - 14:20 An IPC Control Mechanism for Real-Time Processing on a Prioritized SMT Processor Kensuke Kaneda, Kohei Matsumoto, Nobuyuki Yamasaki (Keio Univ) (8)/CPSY 14:20 - 14:45 Extension of ITRON Specification OS for Multithreaded Processors Rikuhei Ueda, Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) ---------------------------------------- Wed, Jan 25 PM Network Applications (14:55 - 16:10) Chair: Nobuki Kajiwara (Renesas Electronics) ---------------------------------------- (1)/CPSY 14:55 - 15:20 Analysis of Power Domain Sizes on Multi-Vdd Variable-Pipeline Router Takeo Nakamura, Hiroki Matsutani (Keio Univ.), Mitihiro Koibuchi (NII), Kimiyoshi Usami (Shibaura Inst. of Tech.), Hideharu Amano (Keio Univ.) (2)/RECONF 15:20 - 15:45 A Proposal of Signal Integrity Improvement Method Using Impedance-reconfiguration Technique Moritoshi Yasunaga, Hiroki Shimada, Shohei Akita, Takuya Adachi, Hidetoshi Ishijima, Yusuke Kuribara (Univ. of Tsukuba) (3)/CPSY 15:45 - 16:10 A bandwidth control scheme based on a traffic analysis for an on-chip router Daiki Yamazaki, Hiroki Matsutani, Nobuyuki Yamasaki (Keio Univ.) ---------------------------------------- Wed, Jan 25 PM Dynamically Reconfigurable Computing and Robots (16:20 - 18:00) Chair: Akihisa Yamada (Sharp) ---------------------------------------- (4)/RECONF 16:20 - 16:45 A Fast Approximate Solution of Energy Efficient Network Topology Using Reconfigurable Processor, STP Akiko Hirao, Hidetoshi Takeshita, Haruka Yonezu, Satoru Okamoto, Naoaki Yamanaka (Keio Univ.) (5)/RECONF 16:45 - 17:10 Architecture and estimation of reconfigurable processor for multimedia processing Asuka Hayashi, Shuu'ichirou Yamamoto, Hideo Maejima (Tokyo Tech) (6)/VLD 17:10 - 17:35 Robot Control Unit by Using Dynamically Reconfigurable SU(3) Spin Circuit Yusaku Yamazaki, Takuya Suzuki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) (7)/VLD 17:35 - 18:00 A Mobile Robot System using Intelligent Circuit in Silicon Takuya Suzuki, Yusaku Yamazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) ---------------------------------------- Thu, Jan 26 AM Hi-level Synthesis and Arithmetic Applications(1) (09:00 - 10:15) Chair: Hiroki Matsutani (Keio Univ.) ---------------------------------------- (8)/VLD 09:00 - 09:25 Merge of Functions in High-Level Synthesis using Assembly Codes as Intermediate Representation Fumiaki Takashima, Nagisa Ishiura, Makoto Orino (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) (9)/VLD 09:25 - 09:50 High-Level Synthesis of Hardware Relinkable to Software Makoto Orino, Nagisa Ishiura (Kwansei Gakuin Univ.), Hiroyuki Tomiyama (Ritsumeikan Univ.), Fumiaki Takashima (Kwansei Gakuin Univ.), Hiroyuki Kanbara (ASTEM RI/KYOTO) (10)/RECONF 09:50 - 10:15 The Estimation and Experiments of The Hardware Design Method from The UML Modeling Diagrams Daiki Kano, Ryota Yamazaki (Tokai Univ), Naohiko Shimizu (Tokai Univ/IP ARCH) ---------------------------------------- Thu, Jan 26 AM Hi-level Synthesis and Arithmetic Applications(2) (10:25 - 11:40) Chair: Hiroyuki Tomiyama (Ritsumeikan Univ.) ---------------------------------------- (11)/VLD 10:25 - 10:50 Interconnect Reduction in Binding Procedure of HLS Hao Cong, Song Chen, Takeshi Yoshimura (Waseda Univ.) (12)/VLD 10:50 - 11:15 A residue - weighted number conversion algorithm based on signed-digit arithmetic for a three-moduli set Masaya Arai, Yuuki Tanaka, Shugang Wei (Gunma Univ.) (13)/VLD 11:15 - 11:40 Error Checker using Binary tree structure of Residue Signed-Digit Additions Qian Liu, Kazuhiro Motegi, Shugang Wei (Gunma Univ.) ---------------------------------------- Thu, Jan 26 PM GPU and HPC (12:40 - 15:10) Chair: Hideharu Amano(Keio Univ.) ---------------------------------------- (14)/CPSY 12:40 - 13:05 Discussion of Performance Prediction Model for Symmetric Block Ciphers on CUDA Naoki Nishikawa, Keisuke Iwai, Takakazu Kurokawa (NDA) (15)/RECONF 13:05 - 13:30 Fine-grained Adaptive Power Management for Energy Efficient GPU computing Makoto Murasaki, Tsuyoshi Hamada, Felipe A. Cruz (NACC) (16)/CPSY 13:30 - 13:55 development and evaluation of ParaRuby: a distributed GPGPU framework using Ruby Ryo Nakamura, Masato Yoshimi, Mitsunori Miki (Doshisha Univ.) (17)/CPSY 13:55 - 14:20 Implementation and its Evaluation of Distributed PC Grid System Junji Umemoto, Hiroyuki Ebara, Bunryu U (Kansai Univ.) (18)/VLD 14:20 - 14:45 Implementation of Numerical Circuit on 3D FPGA-Array Kenichi Takahashi, Jiang Li, Yusuke Atsumari, Shunsuke Shimazaki, Hakaru Tamukoh, Masatoshi Sekine (TUAT) (19)/RECONF 14:45 - 15:10 Partial Reconfiguration and Its Application on a PC-FPGA Hybrid Cluster Ryo Ozaki, Akira Uejima, Masaki Kohata (Okayama Univ. of Sci.) ---------------------------------------- Thu, Jan 26 PM Reconfigurable Devices (15:25 - 17:05) Chair: Moritoshi Yasunaga (Univ. of Tsukuba) ---------------------------------------- (20)/RECONF 15:25 - 15:50 Evaluation of Improvement Techniques for Placement and Routing on MPLD : a New Reconfigurable Device Ken Taomoto, Masato Inagi, Hideyuki Kawabata, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Masayuki Sato, Takashi Ishiguro (Taiyo Yuden), Toshiaki Kitamura, Masatoshi Nakamura (Hiroshima City Univ) (21)/RECONF 15:50 - 16:15 0.18 um process optically reconfigurable gate array VLSI Takahiro Watanabe, Minoru Watanabe (Shizuoka Univ.) (22)/RECONF 16:15 - 16:40 Recovery experiments from a laser array failure in an optically reconfigurable gate array using a reconfiguration speed-adjustment analog bit Takashi Yoza, Minoru Watanabe (Shizuoka Univ.) (23)/VLD 16:40 - 17:05 Study of pattern area and reconfigurable logic circuit with DG/CNT transistor Takamichi Hayashi, Shigeyoshi Watanabe (SIT) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. # CONFERENCE ANNOUNCEMENT: - We will have a party on Jan. 25th. Fee is 5,000Yen for non-students, and 3,000Yen for Student. If you want to join the party, please send an e-mail to vld-party1201@vlsi.es.kit.ac.jp using the form in the Japanese page. === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Fri, Mar 2, 2012 - Sat, Mar 3, 2012: [Mon, Jan 16] Tue, Apr 10, 2012: [Wed, Feb 15] # SECRETARY: Akira ASATO (FUJITSU) TEL +81-44-754-3233, FAX +81-44-754-3214 E-mail: a          === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Tue, Mar 6, 2012 - Wed, Mar 7, 2012: B-con Plaza [Thu, Dec 8], Topics: Design Methodologies for System-on-a-chip # SECRETARY: Kazutoshi Kobayashi (Kyoto Institute of Technology) E-mail:     ba  t Tel: +81-75-724-7452 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Shorin Kyo (Renesas Electronics Corp.) E-mail: s   nk wz  sTEL: +81-44-435-5446 FAX: +81-44-435-5432 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Fri, Mar 2, 2012 - Sat, Mar 3, 2012: [Mon, Jan 16] # SECRETARY: Nozomu Togawa (Waseda University) Email sldm2011 g    Last modified: 2012-01-26 09:33:37 |
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