Conference Date |
Tue, Jun 8, 2021 13:00 - 17:00
Wed, Jun 9, 2021 09:30 - 17:00 |
Topics |
Reconfigurable system, etc. |
Conference Place |
Online (Zoom) |
Contact Person |
Yoshiki YAMAGUCHI, University of Tsukuba |
Notes on Review |
This article is a technical report without peer review, and its polished version will be published elsewhere. |
Registration Fee |
This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on RECONF. |
Tue, Jun 8 PM Invited Talk (1) 13:00 - 13:50 |
(1) |
13:00-13:50 |
[Invited Talk]
Basics, Applications, and International Standardization of Physically Unclonable Functions (PUFs) |
Yohei Hori (AIST) |
|
13:50-14:10 |
Break ( 20 min. ) |
Tue, Jun 8 PM Memory Access Optimizations 14:10 - 15:25 |
(2) |
14:10-14:35 |
|
|
(3) |
14:35-15:00 |
Development of a simulator to explore the accelerator architecture for breadth-first search. |
Yushi Haraguchi, Kazuya Tanigawa (HCU), Takaaki Miyajima, Jens Huthmann, Kentarou Sano (RIKEN), Tetsuo Hironaka (HCU) |
(4) |
15:00-15:25 |
|
|
|
15:25-15:45 |
Break ( 20 min. ) |
Tue, Jun 8 PM AI accelerators and those applications 15:45 - 17:00 |
(5) |
15:45-16:10 |
A Case for FPGA Implementation of Deep Neural Network Based 2D Point Cloud Registration |
Keisuke Sugiura, Hiroki Matsutani (Keio Univ.) |
(6) |
16:10-16:35 |
Automatic generation of executable code for ReNA |
Yuta Masuda, Yasuhiro Nakahara, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.) |
(7) |
16:35-17:00 |
|
|
Wed, Jun 9 AM Image Processing 09:30 - 10:45 |
(8) |
09:30-09:55 |
|
|
(9) |
09:55-10:20 |
|
|
(10) |
10:20-10:45 |
|
|
|
10:45-11:00 |
Break ( 15 min. ) |
|
11:00-13:00 |
Lunch break (RECONF Research Committee meeting will be held.) ( 120 min. ) |
Wed, Jun 9 PM Invited Talk (2) 13:00 - 13:50 |
(11) |
13:00-13:50 |
[Invited Talk]
Large-scale combinatorial optimization in real-time systems by FPGA-based accelerators for simulated bifurcation |
Kosuke Tatsumura (TOSHIBA) |
|
13:50-14:10 |
Break ( 20 min. ) |
Wed, Jun 9 PM FPGA Application 14:10 - 15:25 |
(12) |
14:10-14:35 |
|
|
(13) |
14:35-15:00 |
Size-independent high-speed FPGA implementation of Gaussian-Jordan method using recursive function calls with C++ templates |
Yuuki Katsusaka, Atsushi Kubota, Tetsuo Hironaka (Hiroshima City Univ.) |
(14) |
15:00-15:25 |
An implementation of a satisfiability problem solver : Amoeba SAT on M-KUBOS board |
Yan Ying Jie, Masashi Aono, Hideharu Amano (Keio Univ.), Kaori Ohkoda, Shingo Fukuda, Saito Kenta (Amoeba Energy), Seiya Kasai (Hokkaido Univ.) |
|
15:25-15:45 |
Break ( 20 min. ) |
Wed, Jun 9 PM FPGA System 15:45 - 17:00 |
(15) |
15:45-16:10 |
|
|
(16) |
16:10-16:35 |
Development of the SYCL interface for FPGA clusters and evaluation of CPU-FPGA collaboration |
Satoshi Kaneko, Hiroyuki Takizawa (Tohoku Univ.), Kentaro Sano (RIKEN) |
(17) |
16:35-17:00 |
A 64-bit RISC-V many-core architecture on FPGAs |
Qixiang Gao, Yoshiki Yamaguchi (Univ. of Tsukuba) |