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| Chair |
|
Kazutoshi Wakabayashi (NEC) |
| Vice Chair |
|
Atsushi Takahashi (Tokyo Inst. of Tech.) |
| Secretary |
|
Ichiro Kohno (Renesas), Nozomu Togawa (Waseda Univ.) |
|
| Conference Date |
Mon, Sep 29, 2008 13:30 - 17:05
Tue, Sep 30, 2008 10:00 - 15:25 |
| Topics |
Physical Design, etc. |
| Conference Place |
The Kanazawa Chamber of Commerce and Industry |
| Transportation Guide |
http://www.kanazawa-cci.or.jp/guidance/position.html |
Contact
Person |
Prof. Mineo Kaneko
0761-51-1276 |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Mon, Sep 29 PM
13:30 - 14:30 |
| (1) |
13:30-14:30 |
[Invited Talk]
Phase-Adjustable Error Detection Flip-Flops with 2-Stage Hold Driven Optimization and Slack Based Grouping Scheme for Dynamic Voltage Scaling  VLD2008-47 |
Masanori Kurimoto, Hiroaki Suzuki (Renesas Technology), Rei Akiyama, Tadao Yamanaka, Haruyuki Okuma (Renesas Design), Hidehiro Takata, Hirofumi Shinohara (Renesas Technology) |
| |
14:30-14:45 |
Break ( 15 min. ) |
Mon, Sep 29 PM
14:45 - 15:35 |
| (2) |
14:45-15:10 |
A DFG Mapping Algorithm for Flexible Engine/Generic ALU Array VLD2008-48 |
Masayuki Honma, Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) |
| (3) |
15:10-15:35 |
FFT Design for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm VLD2008-49 |
Ryo Tamura, Masayuki Honma, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi, Ltd.) |
| |
15:35-15:50 |
Break ( 15 min. ) |
Mon, Sep 29 PM
15:50 - 17:05 |
| (4) |
15:50-16:15 |
Schedulable Resouce Binding under Skew Optimization VLD2008-50 |
Takayuki Obata, Mineo Kaneko (JAIST) |
| (5) |
16:15-16:40 |
Delay Variation-Aware Datapath Synthesis Based on Register Clustering VLD2008-51 |
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) |
| (6) |
16:40-17:05 |
Design and Evalution of a Butterfly Circuit Using Selector Logic by Bit-Level Transformation VLD2008-52 |
Takeshi Namura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Motonobu Tonomura (Dai Nippon Print) |
Tue, Sep 30 AM
10:00 - 11:00 |
| (7) |
10:00-11:00 |
[Invited Talk]
On the Order Statistics Applications to EDA, including Non Parametric Statistical Static Timing Analysis VLD2008-53 |
Masanori Imai (STARC/Tokyo Inst. Tech.) |
| |
11:00-11:15 |
Break ( 15 min. ) |
Tue, Sep 30 AM
11:15 - 12:05 |
| (8) |
11:15-11:40 |
Overlap-aware Analytical Placement Based on Stable-LSE VLD2008-54 |
Naoto Funatsu, Yasuhiro Takashima (Univ. of Kitakyushu) |
| (9) |
11:40-12:05 |
A Routing Method based on Nearest Via Assignment for 2-Layer Ball Grid Array Packages VLD2008-55 |
Yoshiaki Kurata, Yoichi Tomioka, Yukihide Kohira, Atsushi Takahashi (Tokyo Tech) |
| |
12:05-13:30 |
Lunch Break ( 85 min. ) |
Tue, Sep 30 PM
13:30 - 14:20 |
| (10) |
13:30-13:55 |
Fast configuration experiments of a large-gates optically reconfigurable gate array VLD2008-56 |
Mao Nakajima, Minoru Watanabe (Shizuoka Univ.) |
| (11) |
13:55-14:20 |
Fast dynamic optically reconfigurable gate array VLSI VLD2008-57 |
Shinichi Kato, Minoru Watanabe (Shizuoka Univ.) |
| |
14:20-14:35 |
Break ( 15 min. ) |
Tue, Sep 30 PM
14:35 - 15:25 |
| (12) |
14:35-15:00 |
A programmable multi-context optical reconfigurable gate array using a PAL-SLM VLD2008-58 |
Shinya Kubota, Minoru Watanabe (Shizuoka Univ.) |
| (13) |
15:00-15:25 |
Variable linear transconductance OTA VLD2008-59 |
Masaki Ikemoto, Cong-Kha Pham (UEC) |
| Contact Address and Latest Schedule Information |
| VLD |
Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
|
| Contact Address |
Ichiro Kohno (Renesas Technology Corp.)
E- :  h  i      s
TEL: +81-42-312-5873 |
| Announcement |
See also VLD's homepage:
http://www.ieice.org/~vld/ |
Last modified: 2008-07-18 20:05:32
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