Mon, Feb 29 PM
13:30 - 14:45 |
| (1) |
13:30-13:55 |
Tool Support for Verifying Large Scale Hardware Design with Verilog-HDL |
Yuta Morimitsu, Tomoyuki Yokogawa (Okayama Prefectural Univ.), Masafumi Kondo, Hisashi Miyazaki (Kawasaki Univ. of Medical Welfare), Yoichiro Sato, Kazutami Arimoto (Okayama Prefectural Univ.), Norihiro Yoshida (Nagoya Univ.) |
| (2) |
13:55-14:20 |
Random Testing of C Compilers Based on Test Program Generation by Equivalence Transformation |
Kazuhiro Nakamura, Nagisa Ishiura (Kwansei Gakuin Univ.) |
| (3) |
14:20-14:45 |
Task Allocation Methods based on the Maximum Task Parallelism for Multi-core Systems with the DTTR Scheme |
Hiroshi Saito (Univ. Aizu), Masashi Imai (Hirosaki Univ.), Tomohiro Yoneda (NII) |
| |
14:45-15:00 |
Break ( 15 min. ) |
Mon, Feb 29 PM
15:00 - 16:40 |
| (4) |
15:00-15:25 |
High-Level Synthesis of Embedded Systems Controller from Erlang |
Hinata Takabeyashi, Nagisa Ishiura, Kagumi Azuma (Kwansei Gakuin Univ), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) |
| (5) |
15:25-15:50 |
A Multi-Paradigm High-Level Hardware Design Environment |
Shinya Takamaeda (NAIST) |
| (6) |
15:50-16:15 |
ILP Based Synthesis of Soft-Error Tolerant Datapaths Considering Adjacency Constraint between Components |
Junghoon Oh, Mineo Kaneko (JAIST) |
| (7) |
16:15-16:40 |
A Note on the Optimization for Multi-Domain Latch-Based High-Level Synthesis |
Keisuke Inoue (KTC), Mineo Kaneko (JAIST) |
Tue, Mar 1 AM
09:00 - 10:15 |
| (8) |
09:00-09:25 |
A Packet Lookup Engine LSI Based on Mismatch Detection and Hash Search |
Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Naoki Miura, Masami Urano, Satoshi Shigematsu (NTT), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) |
| (9) |
09:25-09:50 |
A Screening Circuit for Intrusion Detection of High-Speed Networks and its FPGA Implementation |
Hiroki Takaguchi, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.) |
| (10) |
09:50-10:15 |
Evaluation of Rotator-based Multiplexer Network with Control Circuits for Field-data Extractors |
Koki Ito, Kazushi Kawamura (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Tue, Mar 1 AM
10:30 - 12:10 |
| (11) |
10:30-10:55 |
Electromagnetic Analysis Attack for Simeck and Simon |
Yusuke Nozaki, Masaya Yoshikawa (Meijo Univ.) |
| (12) |
10:55-11:20 |
Power Analysis Attack for Countermeasure with Check Circuit |
Yoshiya Ikezaki, Masaya Yoshikawa (Meijo Univ.) |
| (13) |
11:20-11:45 |
Timing-error-tolerant AES Cipher |
Shinnosuke Yoshida, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
| (14) |
11:45-12:10 |
In-situ Hardware-Trojan Authentication for Invalidating Malicious Functions |
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
| |
12:10-13:30 |
Break ( 80 min. ) |
Tue, Mar 1 PM
13:30 - 14:30 |
| (15) |
13:30-14:30 |
[Invited Talk]
VLSI Technology for Embedded Systems in the More than Moore Era
-- Focusing on Leading Edge Medical Applications -- |
Masaharu Imai, Yoshinori Takeuchi (Osaka Univ.) |
| |
14:30-14:45 |
Break ( 15 min. ) |
Tue, Mar 1 PM
14:45 - 16:00 |
| (16) |
14:45-15:10 |
IP Design using High-Level Synthesis Design Flow |
Masato Tatsuoka, Ken Imanishi, Hidenori Nakaishi, Takeshi Toyoyama (SNI) |
| (17) |
15:10-15:35 |
FPGA Implementation of a Distributed-register Architecture Circuit Using floorplan-aware High-level Synthesis |
Koichi Fujiwara, Kawamura Kazushi, Keita Igarashi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
| (18) |
15:35-16:00 |
The System Performance Evaluation and the FPGA Top-down Design with High-level Design |
Koki Murano, Koji Miyanohana, Tetsuya Takeo, Tsutomu Motohama, Noriyuki Minegishi (Mitsubishi Elec.) |
| |
16:00-16:15 |
Break ( 15 min. ) |
Tue, Mar 1 PM
16:15 - 17:30 |
| (19) |
16:15-16:40 |
Noise reduction effect for input dependence of Zigzag Power Gating |
Tadahiro Kanamoto, Kimiyoshi Usami (Shibaura Institute of Tech.) |
| (20) |
16:40-17:05 |
Optimization technique of substrate voltage for Dynamic Multi-Vth methodology in Silicon-on-thin BOX. |
Hanano Suzuki, Kimiyoshi Usami (Shibaura IT) |
| (21) |
17:05-17:30 |
Low-power Standard Cell Memory using Silicon-on-Thin-BOX (SOTB) and Body-bias Control |
Yusuke Yoshida, Masaru Kudo, Kimiyoshi Usami (SIT) |
Tue, Mar 1 PM
17:30 - 17:55 |
| (22) |
17:30-17:55 |
[Memorial Lecture]
A Closed-Form Stability Model for Cross-Coupled Inverters Operating in Sub-Threshold Voltage Region |
Tatsuya Kamakari, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ.) |
| |
- |
Banquet |
Wed, Mar 2 AM
09:00 - 10:15 |
| (23) |
09:00-09:25 |
FPGA Design and Evaluation of Volume Rendering Circuits Using Selector Logic |
Keita Igarashi, Masao Yanagisawa, Togawa Nozomu (Waseda Univ.) |
| (24) |
09:25-09:50 |
An FPGA Implementation of Fast 2D-Ising-Model Solver for the Max-Cut Problem |
Hidenori Gyoten, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) |
| (25) |
09:50-10:15 |
A Low-Power Intelligent Camera using an FPGA toward Internet of Things Agriculture |
Takahisa Kurose, Hiroki Nakahara, Tetsuo Morimoto (Ehime Univ.) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Wed, Mar 2 AM
10:30 - 11:45 |
| (26) |
10:30-10:55 |
Self-Aligned Quadruple Patterning-Aware Three-Color Grid Routing with Different Color Net |
Toshiyuki Hongo, Atsushi Takahashi (Tokyo Tech) |
| (27) |
10:55-11:20 |
Lithography Hotspot Detection Using Histogram of Oriented Light Propagation |
Yoichi Tomioka (UoA), Tetsuaki Matsunawa (Toshiba) |
| (28) |
11:20-11:45 |
Performance Improvement by Engineering Change Order in General-Synchronous Framework for Altera FPGA |
Hayato Mashiko, Takuya Oba, Yukihide Kohira (Univ. of Aizu) |
| |
11:45-13:00 |
Break ( 75 min. ) |
Wed, Mar 2 PM
13:00 - 14:40 |
| (29) |
13:00-13:25 |
An Algorithm for Reducing Components of a Gaussian Mixture Model 1
-- A Partitioning Method of Components -- |
Naoya Yokoyama, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.) |
| (30) |
13:25-13:50 |
An Algorithm for Reducing Components of a Gaussian Mixture Model 2
-- A Method for Calculating Sensitivities -- |
Daiki Azuma, Shuji Tsukiyama (Chuo Univ.), Masahiro Fukui (Ritsumeikan Univ.), Takashi Kambe (Kinki Univ.) |
| (31) |
13:50-14:15 |
Acceleration of General Synchronous Circuits by Variable Latency Technique using Dynamic Timing-Error Detection |
Hiroshi Nakatsuka, Atsushi Takahashi (Tokyo Tech) |
| (32) |
14:15-14:40 |
Resource Binding in Datapath Synthesis for Performance Enhancement by Post-Silicon Skew Tuning |
Kazuho Katsumata, Mineo Kaneko (JAIST) |
: ht
fc
i