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Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Hiroshi Takahashi (Ehime Univ.)
Vice Chair Tatsuhiro Tsuchiya (Osaka Univ.)
Secretary Masayuki Arai (Nihon Univ.), Kazuteru Namba (Chiba Univ.)

Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Daisuke Fukuda (Fujitsu Labs.)
Vice Chair Kazutoshi Kobayashi (Kyoto Inst. of Tech.)
Secretary Yuichi Sakurai (Hitachi), Daisuke Kanemoto (Osaka Univ.)
Assistant Takuma Nishimoto (Hitachi)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Makoto Nagata (Kobe Univ.)
Vice Chair Masafumi Takahashi (masafumi2.takahashi@kioxia.com)
Secretary Masatoshi Tsuge (Socionext), Tetsuya Hirose (Osaka Univ.)
Assistant Koji Nii (TSMC), Kosuke Miyaji (Shinshu Univ.), Takeshi Kuboki (Kyushu Univ.)

Technical Committee on Reconfigurable Systems (RECONF) [schedule] [select]
Chair Yuichiro Shibata (Nagasaki Univ.)
Vice Chair Kentaro Sano (RIKEN), Yoshiki Yamaguchi (Tsukuba Univ.)
Secretary Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)
Assistant Hiroki Nakahara (Tokyo Inst. of Tech.), Yukitaka Takemura (INTEL)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yuichi Nakamura (NEC)
Secretary Kenshu Seto (Tokyo City Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Kazuki Oya (Mitsubishi Electric), Masayuki Hiromoto (Fujistu Lab.)

Conference Date Tue, Nov 17, 2020 09:30 - 15:40
Wed, Nov 18, 2020 09:30 - 15:15
Topics Design Gaia 2020 -New Field of VLSI Design- 
Conference Place  
Sponsors This conference is co-sponsored by IEEE CEDA All Japan Joint Chapter; IEEE CASS Japan Joint Chapter .
Registration Fee This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on VLD, DC, RECONF, ICD.

Tue, Nov 17 AM 
09:30 - 10:20
(1)
ICD
09:30-09:55 Design of Nonvolatile SRAM Using SONOS Flash Cell and its Evaluation by Circuit Simulation Takaki Urabe, Koji Nii, Kazutoshi Kobayashi (KIT)
(2)
ICD
09:55-10:20 A Study on Power Gating Switch Control Technique for Nonvolatile Logic LSI Fangcen Zhong, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.)
Tue, Nov 17 AM 
10:30 - 11:45
(3)
DC
10:30-10:55 Power Analysis Based on Probability Calculation of Small Regions in LSI Ryo Oba, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech)
(4)
DC
10:55-11:20 DET Flip-Flops with SEU Detection Capability Using DICE and C-Element Xu Haijia, Kazuteru Namba (Chiba Univ.)
(5)
DC
11:20-11:45 Control Point Selection Approach for Scan Pattern Reduction under Multi-cycle Test Hikaru Tamaki, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas)
  11:45-13:00 Lunch Break ( 75 min. )
Tue, Nov 17 PM 
13:00 - 14:00
(6)
RECONF
13:00-14:00 [Keynote Address]
Prospect of Large-Scale Neural-Network Simulation by Exa-scale Computing
Jun Igarashi (RIKEN)
Tue, Nov 17 PM 
14:00 - 15:15
(7)
RECONF
14:00-14:25
(8)
RECONF
14:25-14:50 Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder Naoto Soga, Shimpei Sato, HIroki Nakahara (Tokyo Tech)
(9)
RECONF
14:50-15:15
Tue, Nov 17 AM 
09:30 - 11:10
(10)
VLD
09:30-09:55 Analysis of Resistance Distribution in Chips with Inductive Coupling Wireless Communication Interface Hideto Kayashima, Hideharu Amano, Tsunaaki Shidei (Keio Univ.)
(11)
VLD
09:55-10:20 Efficient computation of inductive invariant through flipflop selection Fudong Wang, Masahiro Fujita (U-Tokyo)
(12)
VLD
10:20-10:45 R-GCN Based Function Inference for An Arithmetic Circuit Yuichiro Fujishiro, Motoki Amagasaki, Masahiro Iida (Kumamoto Univ.), Hiroto Ito, Daisuke Ido (MITSUBISHI ELECTRIC ENGINEERING)
(13)
VLD
10:45-11:10 Implementation of YOLO in the AI accelerator ReNA Toma Uemura, Yasuhiro Nakahara, Motoki Amagasaki, Masato Kiyama, Masahiro Iida (Kumamoto Univ.)
  11:10-14:00 Lunch Break ( 170 min. )
Tue, Nov 17 PM 
14:00 - 15:40
(14)
VLD
14:00-14:25 Quantum Circuit Design by Steiner-Gauss with Considering the Order of Qubits Zhengtong Han, Shigeru Yamashita (Ritsumei Univ.)
(15)
VLD
14:25-14:50 Variable Ordering for Minimizing Power Consumption of BDD-based Optical Logic Circuits Ryosuke Matsuo, Shin-ichi Minato (Kyoto Univ)
(16)
VLD
14:50-15:15 Restricted-Area and Fast Sample Preparation of a Fluid using Programmable Microfluidic Devices Ou Suiketsu, Yamashita Shigeru (Ritsumei Univ.), Sudip Roy (Indian Institute of Technology (IIT) Roorkee), Juinn-Dar Huang (National Chiao Tung University)
(17)
VLD
15:15-15:40 Transformation of Mixing Graphs Considering Splitting Errors on Digital Microfluidic Biochip Ikuru Yoshida, Shigeru Yamashita (Ritsumeikan Univ.)
Wed, Nov 18 AM 
09:30 - 10:45
(18)
ICD
09:30-09:55 Study on Design Guidelines for Low Power Capsule Endoscope System Using Compressed Sensing Yuuki Harada, Daisuke Kanemoto (Osaka Univ.), Makoto Ohki (Yamanashi Univ.), Osamu Maida, Tetsuya Hirose (Osaka Univ.)
(19)
ICD
09:55-10:20 Column-Parallel Pipelined ADC with Ring Amplifier for High Speed and High Spatial Resolution CMOS Image Sensor Takashi Kojima (TUS), Toshinori Otaka, Yusuke Kameda, Takayuki Hamamoto (TUS)
(20)
ICD
10:20-10:45
  10:45-13:35 Lunch Break ( 170 min. )
Wed, Nov 18 PM 
14:00 - 15:15
(21)
ICD
14:00-14:25 Measurement Results of Total Ionizing Dose Effect on Ring Oscillators Fabricated by a Thin-BOX FDSOI Process for Outer-space Mission Takashi Yoshida, Jun Furuta, Kazutoshi Kobayashi (KIT)
(22)
ICD
14:25-14:50 On-chip power supply noise monitoring for evaluation of multi-chip board power delivery networks Daichi Nakagawa, Kazuki Yasuda, Masaru Mashiba, Kazuki Monta, Takaaki Okidono, Takuji Miki, Makoto Nagata (Kobe Univ)
(23)
ICD
14:50-15:15 Evaluation of operating performance of ECDSA hardware module II Yuya Takahashi, Takuya Matsumaru, Kazuki Monta (Kobe Univ.), Toshihiro Sato, Takaaki Okidono (ECSEC Lab), Takuji Miki, Noriyuki Miura, Makoto Nagata (Kobe Univ.)
Wed, Nov 18 AM 
09:30 - 10:45
(24)
VLD
09:30-09:55 Comparing RISC-V RV32I and MIPS R3000 as a model processor for education Hideharu Amano, Kensuke Iizuka, Kohei Itoh (Keio Univ.)
(25)
VLD
09:55-10:20 Seat Layout Method Considering Physical Distance Using Cell Placement Methods in LSI Yukihide Kohira (Univ. of Aizu)
(26)
VLD
10:20-10:45 N/A Tomoya Wakaizumi, Kazunari Takasaki, Yuta Yachi, Tomokazu Yoshimura, Makoto Nishizawa, Masashi Tawada, Nozomu Togawa (Waseda Univ.)
Wed, Nov 18 AM 
11:00 - 11:50
(27) 11:00-11:25  
(28) 11:25-11:50  
  11:50-13:00 Lunch Break ( 70 min. )
Wed, Nov 18 PM 
13:00 - 14:00
(29)
VLD
13:00-14:00 [Keynote Address]
Quality Assurances of the Fugaku Supercomputer: Function, Performance and Power
Takahide Yoshikawa (FLAB)
Wed, Nov 18 PM 
14:00 - 14:50
(30)
VLD
14:00-14:25 Physically Unclonable Functions(PUF) curcuit using Non-Volatile Flip-Flop and security evaluation against modeling attacks Hiroki Ishihara, Kimiyoshi Usami (Shibaura IT)
(31)
VLD
14:25-14:50 Energy Efficient Approximate Storing of Image Data for Non-volatile Memory Yoshinori Ono, Kimiyoshi Usami (SIT)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address  
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address  
Announcement See also VLD's homepage:
http://www.ieice.org/~vld/
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address  
RECONF Technical Committee on Reconfigurable Systems (RECONF)   [Latest Schedule]
Contact Address  
Announcement http://www.ieice.org/~reconf/
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Kenshu Seto (Tokyo City University)
E--mail: ktcu 
Announcement Please see the IPSJ-SLDM page below:
http://www.sig-sldm.org/


Last modified: 2020-11-16 11:16:57


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