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=============================================== Technical Committee on Dependable Computing (DC) Chair: Tomohiro Yoneda (NII) Vice Chair: Seiji Kajihara (Kyushu Inst. of Tech.) Secretary: Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas) =============================================== Technical Committee on Computer Systems (CPSY) Chair: Shuichi Sakai (Univ. of Tokyo) Vice Chair: Yoshio Miki (Hitachi), Hideharu Amano (Keio Univ.) Secretary: Morihiro Kuga (Kumamoto Univ.), Hiroshi Ueno (NEC) Assistant: Hidetsugu Irie (Univ. of Electro-Comm.) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Kazutoshi Wakabayashi Secretary: Naoyuki Hoshi, Naohito Kojima, Kenshu Seto =============================================== Special Interest Group on Embedded Systems (IPSJ-EMB) Chair: Yukikazu Nakamoto Secretary: 久保秋 真, Eiichi Hayakawa, Atsushi Sawada DATE: Fri, Mar 18, 2011 09:40 - 17:15 Sat, Mar 19, 2011 09:00 - 16:00 PLACE: TOPICS: ---------------------------------------- Fri, Mar 18 AM (09:40 - 11:45) ---------------------------------------- (1) 09:40 - 10:05 (2) 10:05 - 10:30 (3) 10:30 - 10:55 (4) 10:55 - 11:20 (5) 11:20 - 11:45 ---------------------------------------- Fri, Mar 18 AM (09:40 - 11:45) ---------------------------------------- (6)/DC 09:40 - 10:05 Examination of network fault detection method by use of AFM Isao Shimokawa, Toshiaki Tarui, Hiroki Miyamoto, Tomohiro Baba (hitachi) (7)/DC 10:05 - 10:30 Diagnosis for Automotive Electronic Control System -- Extraction of Singular Relation from CAN data with WPMax-SAT -- Shuichi Sato, Takuro Kutsuna (TCRDL), Naoya Chujo (AIT), Noriyoshi Sano (TCRDL) (8)/DC 10:30 - 10:55 Development of a Network Recorder for High-Speed Real-Time Data Acquisition and Packet Capture Kenji Toda, Mamoru Sekiyama (AIST) (9)/DC 10:55 - 11:20 Modeling of Timing Faults and Test Generation for Single Flux Quantum Logic Circuits Nobutaka Kito (Kyoto Univ.), Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) (10)/DC 11:20 - 11:45 Design Method of Easily Testable Parallel Adders under Delay Constraints Shinichi Fujii (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.) ----- Lunch ( 75 min. ) ----- ---------------------------------------- Fri, Mar 18 PM (13:00 - 14:15) ---------------------------------------- (11) 13:00 - 13:25 (12) 13:25 - 13:50 (13) 13:50 - 14:15 ---------------------------------------- Fri, Mar 18 PM (13:25 - 14:15) ---------------------------------------- (14) 13:25 - 13:50 (15) 13:50 - 14:15 ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Mar 18 PM (14:30 - 15:45) ---------------------------------------- (16) 14:30 - 14:55 (17) 14:55 - 15:20 (18) 15:20 - 15:45 ---------------------------------------- Fri, Mar 18 PM (14:30 - 15:45) ---------------------------------------- (19) 14:30 - 14:55 (20) 14:55 - 15:20 (21) 15:20 - 15:45 ----- Break ( 15 min. ) ----- ---------------------------------------- Fri, Mar 18 PM (16:00 - 17:15) ---------------------------------------- (22) 16:00 - 16:25 (23) 16:25 - 16:50 (24) 16:50 - 17:15 ---------------------------------------- Fri, Mar 18 PM (16:00 - 17:15) ---------------------------------------- (25) 16:00 - 16:25 (26) 16:25 - 16:50 (27) 16:50 - 17:15 ----- ----- ---------------------------------------- Sat, Mar 19 AM (09:00 - 10:40) ---------------------------------------- (28) 09:00 - 09:25 (29) 09:25 - 09:50 (30) 09:50 - 10:15 (31) 10:15 - 10:40 ---------------------------------------- Sat, Mar 19 AM (09:00 - 10:40) ---------------------------------------- (32) 09:00 - 09:25 (33) 09:25 - 09:50 (34) 09:50 - 10:15 (35) 10:15 - 10:40 ----- Break ( 15 min. ) ----- ---------------------------------------- Sat, Mar 19 AM (10:55 - 12:10) ---------------------------------------- (36) 10:55 - 11:20 (37) 11:20 - 11:45 (38) 11:45 - 12:10 ---------------------------------------- Sat, Mar 19 AM (10:55 - 12:10) ---------------------------------------- (39) 10:55 - 11:20 (40) 11:20 - 11:45 (41)/CPSY 11:45 - 12:10 Virtual HILS -- Efficient software validation by entire system virtualization -- Yasuhiro Ito, Yasuo Sugure, Shigeru Oho (HItachi) ----- Lunch ( 65 min. ) ----- ---------------------------------------- Sat, Mar 19 PM (13:15 - 14:30) ---------------------------------------- (42) 13:15 - 13:40 (43) 13:40 - 14:05 (44) 14:05 - 14:30 ---------------------------------------- Sat, Mar 19 PM (13:15 - 14:30) ---------------------------------------- (45)/CPSY 13:15 - 13:40 Performance Evaluation of High Performance Linpack on a Cell/B.E. Cluster with Heterogeneous Interconnect Ryota Nishida, Tetsuya Nakahama, Toshiaki Kamata, Yuri Nishikawa, Hideharu Amano (Keio Univ.) (46)/CPSY 13:40 - 14:05 Implementation and evaluation of Meresenne Twister with massive-parallel SIMD processing Youhei Mochizuki, Naoyuki Yoshida, Naoki Matsumoto, Yuma Murakami, Takeshi Kumaki, Takeshi Fujino (Ritsumeikan Univ.) (47)/CPSY 14:05 - 14:30 A study on parallel cryptographic processing with ultra-compact single-board computer Takeshi Kumaki, Yuichiro Kurokawa, Takeshi Fujino (Ritsumeikan Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Sat, Mar 19 PM (14:45 - 16:00) ---------------------------------------- (48) 14:45 - 15:10 (49) 15:10 - 15:35 (50) 15:35 - 16:00 ---------------------------------------- Sat, Mar 19 PM (14:45 - 16:00) ---------------------------------------- (51)/CPSY 14:45 - 15:10 Parallel C code generation from Simulink models Takahiro Kumura (NEC/Osaka Univ.), Masato Edahiro, Yuichi Nakamura (NEC), Nagisa Ishiura (Kwansei Gakuin Univ.), Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) (52)/CPSY 15:10 - 15:35 An Architecture for Low-Latency Anonymizing Mechanism Junichi Sawada, Koichi Inoue, Hiroaki Nishi (Keio Univ.) (53)/CPSY 15:35 - 16:00 A Cache Control Method for Optimizing Receive Queue with Cache Injection Ryota Mibu, Tomoyoshi Sugawara (NEC) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Dependable Computing (DC) === # FUTURE SCHEDULE: Tue, Apr 12, 2011: [Fri, Feb 11] Mon, May 16, 2011 - Wed, May 18, 2011: Kitakyushu International Conference Center [Fri, Mar 11], Topics: LSI and Systems Workshop Fri, Jun 24, 2011: Kikai-Shinko-Kaikan Bldg. [Fri, Apr 15], Topics: Design, Test, Verification # SECRETARY: Masato Kitakami Graduate School of Advanced Integration Science, Chiba University 1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN TEL/FAX +43.290.3039 E-mail:     f ulty  ba-u === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Tue, Apr 12, 2011: [Fri, Feb 11] Mon, May 16, 2011 - Wed, May 18, 2011: Kitakyushu International Conference Center [Fri, Mar 11], Topics: LSI and Systems Workshop # SECRETARY: Morihiro KUGA (Kumamoto Univ.) TEL +81-96-342-3647, FAX +81-96-342-3599 E-mail:    am  -u === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Mon, May 16, 2011 - Wed, May 18, 2011: Kitakyushu International Conference Center [Fri, Mar 11], Topics: LSI and Systems Workshop Wed, May 18, 2011 - Thu, May 19, 2011: Kitakyushu International Conference Center [Fri, Mar 18], Topics: System Design, etc. === Special Interest Group on Embedded Systems (IPSJ-EMB) === Last modified: 2011-03-13 21:12:35 |
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