IEICE Technical Committee Submission System
Advance Program
Online Proceedings
[Sign in]
Tech. Rep. Archives
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


Technical Committee on Component Parts and Materials (CPM) [schedule] [select]
Chair Kiichi Kamimura (Shinshu Univ.)
Vice Chair Kanji Yasui (Nagaoka Univ. of Tech.)
Secretary Seiji Toyoda (NTT), Hidehiko Shimizu (Niigata Univ.)
Assistant Yasushi Takemura (Yokohama National Univ.), Naoki Oba (NTT)

Technical Committee on Integrated Circuits and Devices (ICD) [schedule] [select]
Chair Akira Matsuzawa (Tokyo Inst. of Tech.)
Vice Chair Kunio Uchiyama (Hitachi)
Secretary Yoshiharu Aimoto (NECEL), Makoto Nagata (Kobe Univ.)
Assistant Minoru Fujishima (Univ. of Tokyo), Yoshio Hirose (Fujitsu Labs.)

Conference Date Thu, Jan 17, 2008 09:15 - 16:35
Fri, Jan 18, 2008 09:40 - 16:35
Topics  
Conference Place  

Thu, Jan 17 AM 
09:15 - 16:35
(1) 09:15-09:40 Non-Contact 10% Efficient 36mW Power Delivery Using On-Chip Inductor in 0.18-um CMOS Yuan Yuxiang, Yoichi Yoshida, Tadahiro Kuroda (keio Univ.)
(2) 09:40-10:05 Integrated evaluation of on-chip power supply noise and off-chip electromagnetic noise on digital LSI Yuki Takahashi (Kobe Univ.), Kouji Ichikawa (Denso), Makoto Nagata (Kobe Univ.)
(3) 10:05-10:30 ptimization of Active Substrate Noise Cancellng Technique Using Multi di/dt Detectors Toru Nakura, Taisuke Kazama, Makoto Ikeda, Kunihiro Asada (The Univ. of Tokyo)
  10:30-10:45 Break ( 15 min. )
(4) 10:45-11:10 All Digital Gated Oscillator for Dynamic Supply Noise Measurement Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye (Osaka Univ.)
(5) 11:10-11:35 Design of an On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai (Univ. of Tokyo)
(6) 11:35-12:00 LSI and PCB Unified Noise Analysis CAD System Toshiro Sato, Hiroyuki Orihara, Shogo Fujimori, Masaki Tosaka (FATEC)
  12:00-13:00 Break ( 60 min. )
(7) 13:00-13:40 [Special Invited Talk]
On-chip monitors and power-supply integrity
Makoto Nagata (Kobe Univ.)
(8) 13:40-14:20 [Special Invited Talk]
Techniques for power supply noise management in the SX supercomputers
Jun Inasaka, Mikihiro Kajita (NEC Corp.)
  14:20-14:30 Break ( 10 min. )
(9) 14:30-15:10 [Special Invited Talk]
In-situ measurement of supply-noise maps with millivolt accuracy and nanosecond-order time resolution
Yusuke Kanno, Yuki Kondoh (HCRL), Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu (Renesas Technology, Corp.), Shigenobu Komatsu, Hiroyuki Mizuno (HCRL)
  15:10-15:25 Break ( 15 min. )
(10) 15:25-16:35  
Fri, Jan 18 AM 
09:40 - 16:35
(11) 09:40-10:05 Arithmetic operation circuit based on abacus architecture Syunsuke Nagasawa, Shugang Wei (Gunma Univ)
(12) 10:05-10:30 A compact RF signal quality measurement macro for RF test and diagnosis Koichi Nose, Masayuki Mizuno (NEC)
(13) 10:30-10:55 A Method for Measuring Vref Noise Tolerance of DDR2-SDRAM on Test Board that Simulates Memory Module Yutaka Uematsu, Hideki Osaka (Hitachi), Yoji Nishio, Susumu Hatano (Elpida)
  10:55-11:10 Break ( 15 min. )
(14) 11:10-12:00 [Tutorial Lecture]
Survey of Analysis Techniques for On-chip Power Distribution Networks
Takashi Sato (Tokyo Tech.)
  12:00-13:00 Lunch Break ( 60 min. )
(15) 13:00-13:25 Study on Low Stress Condition of Pseudo-SOC Integration Using Stress Analysis Yutaka Onozuka, Hiroshi Yamada, Atsuko Iida, Kazuhiko Itaya, Hideyuki Funaki (Toshiba R & D Center)
(16) 13:25-13:50 An Extraction Method of Material Constants by Transmission Line Measurements Hiroshi Toyao, Yoshiaki Wakabayashi (NEC)
(17) 13:50-14:15 A Package-on-Package using Coreless Substrate with Excellent Power Integrity Kentaro Mori, Jun Sakai, Katsumi Kikuchi, Shinji Watanabe, Tomoo Murakami, Shintaro Yamamichi (NEC)
(18) 14:15-14:40 Assessment Test for Solder Joint Reliability in Mobile Products Masazumi Amagai, Hiroyuki Sano (TI Japan)
  14:40-14:55 Break ( 15 min. )
(19) 14:55-15:20 Chip Thinning Technologies Realizing High Chip Strength Shinya Takyu, Tetsuya Kurosawa, Noriko Shimizu, Susumu Harada (Toshiba Co.)
(20) 15:20-15:45 A multi-layer wafer-level 5-um-thick Cu wiring technology with photosensitive resin Katsumi Kikuchi (NEC), Kouji Soejima (NECEL), Yasuhiro Ishii (NEC), Masaya Kawano (NECEL), Masayuki Mizuno, Shintaro Yamamichi (NEC)
(21) 15:45-16:10 A method of Ultra-fine Pad Interconnection using Electroless Deposition Tokihiko Yokoshima, Yasuhiro Yamaji, Yuichiro Tamura, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi (AIST)
(22) 16:10-16:35 Reliability evaluation of lead free solder joint against vibration load under thermal circumstance Michiya Matsushima (Osaka Univ.), Toshiyuki Hamano (ESPEC), Kiyokazu Yasuda, Kozo Fujimoto (Osaka Univ.)

Contact Address and Latest Schedule Information
CPM Technical Committee on Component Parts and Materials (CPM)   [Latest Schedule]
Contact Address Hidehiko Shimizu(Niigata University)
TEL 025-262-6811, FAX 025-262-6811
E--mail: engi-u

Yasushi Takemura(Yokohama National University)
TEL 045-339-4151, FAX 045-339-4151
E--mail: y 
ICD Technical Committee on Integrated Circuits and Devices (ICD)   [Latest Schedule]
Contact Address Yoshiharu Aimoto (NEC Electronics Corporation)
TEL +81-44-435-1258, +81-44-435-1878
E--mail:aicel 


Last modified: 2008-01-04 12:13:48


Notification: Mail addresses are partially hidden against SPAM.

[Download Paper's Information (in Japanese)] <-- Press download button after click here.
 
[Cover and Index of IEICE Technical Report by Issue]
 

[Presentation and Participation FAQ] (in Japanese)
 

[Return to CPM Schedule Page]   /   [Return to ICD Schedule Page]   /  
 
 Go Top  Go Back   / [HTML] / [HTML(simple)] / [TEXT]  [Japanese] / [English] 


[Return to Top Page]

[Return to IEICE Web Page]


The Institute of Electronics, Information and Communication Engineers (IEICE), Japan