Fri, Feb 5 AM 10:30 - 11:20 |
(1) |
10:30-10:55 |
A Study on a Method of Measuring Process Variations Considering the Effect of Wire Delay on FPGA |
Shingo Tsutsumi, Yukiya Miura (Tokyo Metropolitan Univ.) |
(2) |
10:55-11:20 |
Hardware Trojan Detection by Learning Power Side Channel Signals Considering Random Process Variation |
Michiko Inoue, Riaz-Ul-Haque Mian (NAIST) |
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11:20-11:35 |
Break ( 15 min. ) |
Fri, Feb 5 AM 11:35 - 12:50 |
(3) |
11:35-12:00 |
A Novel High Performance Scan-Test-Aware Hardened Latch Design |
Ruijun Ma, Stefan Holst, Xiaoqing Wen (KIT), Aibin Yan (AHU), Hui Xu (AUST) |
(4) |
12:00-12:25 |
Locating High Power Consuming Area in Logic parts Caused by Memory Size and Shapes |
Daiki Takafuji, Ryu Hoshino, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara (Kyutech) |
(5) |
12:25-12:50 |
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12:50-14:00 |
Break ( 70 min. ) |
Fri, Feb 5 PM 14:00 - 15:15 |
(6) |
14:00-14:25 |
Multiple Target Test Generation Method using Test Scheduling Information of RTL Hardware Elements |
Ryuki Asami, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ), Masayuki Arai (Nihon Univ) |
(7) |
14:25-14:50 |
Fault Coverage Estimation Method in Multi-Cycle Testing |
Norihiro Nakaoka, Senling Wang, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.), Hiroyuki Iwata, Yoichi Maeda, Jun Matsushima (Renesas Electronics Corp.) |
(8) |
14:50-15:15 |
A Test Generation Method Using Information of Easily Testable Functional Time Expansion Model |
Kenta Nakamura, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.) |
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15:15-15:30 |
Break ( 15 min. ) |
Fri, Feb 5 PM 15:30 - 16:45 |
(9) |
15:30-15:55 |
A Don't Care Filling Method of Control Signals Based on Non-scan Field Testability at Register Transfer Level |
Yuki Ikegaya, Yuta Ishiyama, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) |
(10) |
15:55-16:20 |
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(11) |
16:20-16:45 |
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