Mon, Feb 14 AM
10:00 - 10:50 |
| (1) |
10:00-10:25 |
The development of the DDR3 memory module tester used on memory test processor |
Takeshi Asakawa, Satoshi Matsuno (Tokai Univ.), Hidekazu Tsuchiya (Hitachi), Tatsuya Seki, Shinichi Kmazawa (Techinica) |
| (2) |
10:25-10:50 |
Capture-Safety Checking Based on Transition-Time-Relation for At-Speed Scan Test Vectors |
Ryota Sakai, Kohei Miyase, Xiaoqing Wen (Kyushu Inst. of Tech.), Masao Aso, Hiroshi Furukawa (RMS), Yuta Yamato (Fukuoka Ind. Sci & Tech/Fundation FIST), Seiji Kajihara (Kyushu Inst. of Tech.) |
| |
10:50-11:00 |
Break ( 10 min. ) |
Mon, Feb 14 AM
11:00 - 12:15 |
| (3) |
11:00-11:25 |
An Analysis of Critical Paths for Field Testing with Process Variation Consideration |
Satoshi Kashiwazaki, Toshinori Hosokawa (Nihon Univ), Masayoshi Yoshimura (Kyushuu Univ) |
| (4) |
11:25-11:50 |
Variation Aware Test Methodology Based on Statistical Static Timing Analysis |
Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo (STARC) |
| (5) |
11:50-12:15 |
A Pattern Generation Method to Uniform Initial Temperature of Test Application |
Emiko Kosoegawa, Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) |
| |
12:15-13:45 |
Lunch Break ( 90 min. ) |
Mon, Feb 14 PM
13:45 - 15:00 |
| (6) |
13:45-14:10 |
Test Pattern Generation for Highly Accurate Delay Testing |
Keigo Hori (NAIST), Tomokazu Yoneda, Michiko Inoue, Hideo Fujiwara (NAIST/JST) |
| (7) |
14:10-14:35 |
A Test Generation Method for Datapath Circuits Using Functional Time Expansion Models |
Teppei Hayakawa, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.) |
| (8) |
14:35-15:00 |
Test Pattern Selection for Defect-Aware Test |
Hiroshi Furutani, Takao Sakai, Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
| |
15:00-15:15 |
Break ( 15 min. ) |
Mon, Feb 14 PM
15:15 - 16:30 |
| (9) |
15:15-15:40 |
An Extended 2-D FPGA Array for CIP Circuit |
Jiang Li, Kenichi Takahashi, Hakaru Tamukoh, Masatoshi Sekine (TUAT) |
| (10) |
15:40-16:05 |
Dual Edge Triggered Flip-Flops for Blocking Noise Pulses on Data Signal Lines |
Yukiya Miura (Tokyo Metropolitan Univ.) |
| (11) |
16:05-16:30 |
Note on Area Overhead Reduction for Reconfigurable On-Chip Debug Circui |
Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.) |
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