===============================================
Technical Committee on VLSI Design Technologies (VLD)
Chair: Shinji Kimura Vice Chair: Hirofumi Hamamura
Secretary: Yusuke Matsunaga, Toshiyuki Shibuya
===============================================
Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)
Chair: Takashi Kambe
Secretary: Masato Edahiro, Mitsuhisa Ohnishi, Kiyoharu Hamaguchi
DATE:
Thu, May 11, 2006 14:00 - 17:00
Fri, May 12, 2006 09:00 - 14:30
PLACE:
Ehime University(Prof. Hiroshi Takahashi. 089-927-9957)
TOPICS:
----------------------------------------
Thu, May 11 PM (14:00 - 16:00)
----------------------------------------
(1) 14:00 - 14:30
Online FPGA Placement Using I/O Routing Information
Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita (NAIST), Kazuo Nakajima (Univ. of Maryland), Katsumasa Watanabe (NAIST)
(2) 14:30 - 15:00
Dynamic Reconfigurable Wiring Architecture and Its Application to Hardware Mapping
Shinji Kimura (Waseda Univ.)
(3) 15:00 - 15:30
A Software-level Energy Reduction Technique for Embedded Microprocessor Exploiting Narrow Bitwidth Operations
Seiichiro Yamaguchi, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
(4) 15:30 - 16:00
Automatic Generation of Custom Instructions with Memory Access and Resource Sharing
Kenshu Seto, Masahiro Fujita (Univ. of Tokyo)
----------------------------------------
Thu, May 11 PM (16:15 - 17:00)
----------------------------------------
(5) 16:15 - 17:00
[Invited Talk]
Configurable Processor Design Environment ASIP Meister
Masaharu Imai, Ittetsu Taniguchi, Yoshinori Takeuchi, Keishi Sakanushi (Osaka Univ.)
----------------------------------------
Fri, May 12 AM (09:00 - 10:30)
----------------------------------------
(6) 09:00 - 09:30
Bottom-up Equivalence Checking for SpecC Programs
Subash Shankar (City Univ. of New York), Masahiro Fujita (Univ. of Tokyo)
(7) 09:30 - 10:00
An Approach to Formal Equivalence Checking by Symbolic Simulation between Behavioral and RTL Designs
Takeshi Matsumoto, Satoshi Komatsu, Masahiro Fujita (Univ. of Tokyo)
(8) 10:00 - 10:30
An Implementation of a Ternary-valued Logic Simulator using a Value-independent Simulator Kernel
Takatomi Wada, Yasushi Hibino (JAIST)
----------------------------------------
Fri, May 12 AM (10:45 - 11:45)
----------------------------------------
(9) 10:45 - 11:15
Efficient generation method of indirect implication on ATPG
Masayoshi Yoshimura (FLEETS), Seiji Kajihara (KIT), Yusuke Matsunaga (Kyushu University)
(10) 11:15 - 11:45
Power-Conscious Microprocessor-Based Testing of System-on-Chip
Fawnizu Azmadi Hussin, Tomokazu Yoneda (NAIST), Alex Orailoglu (Univ. of California), Hideo Fujiwara (NAIST)
----------------------------------------
Fri, May 12 PM (13:00 - 14:30)
----------------------------------------
(11) 13:00 - 13:30
Reduction of Equalizing Circuit Area for 8-VSB Demodulator Using the Result of Correlation Operation
Kazumi Kawashima, Yusuke Konishi, Yusuke Hashiguchi, Yuu Yamamoto, Masahiro Numa (Kobe Univ.)
(12) 13:30 - 14:00
Delay and Power Consumption of Integer Multipiler
-- Comparison of Wallace and Dadda tree --
Masayoshi Tachibana (KUT)
(13) 14:00 - 14:30
Measurement and Analysis of Delay and Power Variations in 90nm CMOS Circuits
Masaki Yamaguchi (Kyushu Univ.), Yang Yuan (Xi'an Univ. of Technology), Kosuke Tarumi, Ryota Sakamoto, Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)
# Information for speakers
General Talk will have 25 minutes for presentation and 5 minutes for discussion.
=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:
Thu, Jun 22, 2006 - Fri, Jun 23, 2006: Kitami Institute of Technology [Fri, Apr 14], Topics: Signal Processing, LSI, etc
# SECRETARY:
Yusuke Matsunaga (Kyushu University)
TEL +81-92-583-7621, FAX +81-92-583-1338
E-mail: matsunaga@ c.csce.kyushu-u.ac.jp
# ANNOUNCEMENT:
# You will see the latest information at the below WEB page.
http://www.ieice.org/vld/index.html
=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) ===
Last modified: 2006-04-18 12:40:00
|
Notification: Mail addresses are partially hidden against SPAM.
|