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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Tetsuo Hironaka (Hiroshima City Univ.)
Vice Chair: Minoru Watanabe (Shizuoka Univ.), Masato Motomura (Hokkaido Univ.)
Secretary: Yutaka Yamada (Toshiba), Yoshiki Yamaguchi (Univ. of Tsukuba)
Assistant: Kazuya Tanikagawa (Hiroshima City Univ.)
DATE:
Wed, Sep 18, 2013 09:00 - 17:50
Thu, Sep 19, 2013 09:00 - 16:05
PLACE:
JAIST(http://www.jaist.ac.jp/general_info/access/index.html. Prof. Yukinori Sato)
TOPICS:
Reconfigurable Systems, etc.
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Wed, Sep 18 AM (09:00 - 11:50)
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(1) 09:00 - 11:50
----- Break ( 70 min. ) -----
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Wed, Sep 18 PM (13:00 - 14:00)
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(2) 13:00 - 14:00
----- Break ( 20 min. ) -----
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Wed, Sep 18 PM (14:20 - 15:10)
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(1) 14:20 - 15:10
[Invited Talk]
Study on Processor Architecture for Image Recognition
Masayuki Miyama (Kanazawa Univ.)
----- Break ( 20 min. ) -----
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Wed, Sep 18 PM (15:30 - 16:45)
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(2) 15:30 - 15:55
An Implementation of High Performance Stream Processing on a Reconfigurable Hardware
Eric Shun Fukuda (Hokkaido Univ.), Hideyuki Kawashima (Univ. of Tsukuba), Hiroaki Inoue (NEC), Taro Fujii, Koichiro Furuta (Renesas Electronics), Tetsuya Asai, Masato Motomura (Hokkaido Univ.)
(3) 15:55 - 16:20
Design and Evaluation of Stream Processor for Incompressive Fluid Computation based on Fractional-Step Method
Ryotaro Chiba, Hayato Suzuki, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
(4) 16:20 - 16:45
A Power-Performance model for 3-D stencil computation on an FPGA accelerator
Keisuke Dohi, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
----- Break ( 15 min. ) -----
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Wed, Sep 18 PM (17:00 - 17:50)
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(5) 17:00 - 17:25
A Restricted Dynamically Reconfigurable Architecture for Low Power Processors
Takeshi Hirao, Dahoo Kim, Itaru Hida, Tetsuya Asai, Masato Motomura (Hokkaido Univ.)
(6) 17:25 - 17:50
Nonvolatile reconfigurable device development platform using a phase change material
Takumi Michida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN)
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Thu, Sep 19 AM (09:00 - 10:15)
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(7) 09:00 - 09:25
A Low power Reconfigurable Accelerator using a Back-gate Bias Control Technique
Hongliang Su, Weihan Wang, Hideharu Amano (Keio Univ.)
(8) 09:25 - 09:50
A LUT Architecture Based on Partial Function of Shannon Expansion
Kyosei Yanagida, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(9) 09:50 - 10:15
Investigation of the area reduction by pass transistor logic in reconfigurable device MPLD
Yuki Yoshida, Takumi Michida, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ.), Kenichi Shimomai, Takashi Ishiguro (TAIYO YUDEN)
----- Break ( 20 min. ) -----
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Thu, Sep 19 AM (10:35 - 11:50)
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(10) 10:35 - 11:00
Hardware Acceleration of Inverted Pendulum Control Processing by Using the High Level Synthesis Tool JavaRock
Daichi Uetake, Takeshi Ohkawa (Utsunomiya Univ.), Takefumi Miyoshi (e-trees), Takashi Yokota, Kanemitsu Ootsu (Utsunomiya Univ.)
(11) 11:00 - 11:25
Design method for hw/sw Complex System
Yuichi Ogishima, Masatoshi Sekine (Tokyo Univ. of Agriculture and Tech.)
(12) 11:25 - 11:50
A Low Power Oriented Design Framework for Considering Reconfiguration Time on Embedded Systems
Koichi Araki, Yukinori Sato, Yasushi Inoguchi (JAIST)
----- Break ( 70 min. ) -----
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Thu, Sep 19 PM (13:00 - 14:40)
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(13) 13:00 - 13:25
The Circuit Configuration method of 3D FPGA-Array System "Vocalise"
Hiromasa Kubo, Jiang Li, Yusuke Atsumari, Baku Ogasawara, Masatoshi Sekine (Tokyo Univ. of Agliculture and Tech.)
(14) 13:25 - 13:50
A study of pipeline execution on PEACH2
Takaaki Miyajima, Takuya Kuhara (Keio Univ.), Toshihiro Hanawa (Tsukuba Univ.), David Thomas (Imperial College), Hideharu Amano (Keio Univ.)
(15) 13:50 - 14:15
A Packet Classifier using Parallel EVMDD(k) Machine
Hiroki Nakahara (Kagoshima Univ.), Tsutomu Sasao (Meiji Univ.), Munehiro Matsuura (Kyushu Inst. of Tech.)
(16) 14:15 - 14:40
Development of Memory Management Framework for FPGA-based Prototyping
Shinya Takamaeda-Yamazaki (Tokyo Inst. of Tech./JSPS Research Fellow), Kenji Kise (Tokyo Inst. of Tech.)
----- Break ( 10 min. ) -----
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Thu, Sep 19 PM (14:50 - 16:05)
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(17) 14:50 - 15:15
Considerations of Constantize for Entries in Associative Memories Using Dynamic Partial Reconfiguration
Tomoaki Ukezono, Koichi Araki (JAIST)
(18) 15:15 - 15:40
Color configuration method for an optically reconfigurable gate array
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
(19) 15:40 - 16:05
Optically reconfigurable gate array with a variable spot-size configuration context
Kouta Akagi, Minoru Watanabe (Shizuoka Univ.)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:
Wed, Nov 27, 2013 - Fri, Nov 29, 2013: [Tue, Sep 17], Topics: Design Gaia 2013 -New Field of VLSI Design-
# SECRETARY:
Shizuoka University
Minoru Watanabe
E-mail: tmwatan [atmark] ipc.shizuoka.ac.jp
TEL: +81-53-478-1096
FAX: +81-53-478-1096
Last modified: 2013-08-29 05:32:55
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