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=============================================== Technical Committee on Silicon Device and Materials (SDM) Chair: Tetsuro Endo (Tohoku Univ.) Vice Chair: Yasuo Nara (Fujitsu Microelectronics) Secretary: Yukinori Ono (NTT), Katsunori Onishi (Kyushu Inst. of Tech.) Assistant: Shintaro Nomura (Univ. of Tsukuba) =============================================== Technical Committee on Integrated Circuits and Devices (ICD) Chair: Kunio Uchiyama (Hitachi) Vice Chair: Masahiko Yoshimoto (Kobe Univ.), Toshihiko Hamasaki (TI) Secretary: Yoshio Hirose (Fujitsu Labs.), Hiroaki Suzuki (Renesas) Assistant: Toshimasa Matsuoka (Osaka Univ.), Ken Takeuchi (Univ. of Tokyo), Kenichi Okada (Tokyo Inst. of Tech.) DATE: Thu, Aug 26, 2010 09:10 - 19:00 Fri, Aug 27, 2010 09:00 - 16:50 PLACE: TOPICS: Low voltage/low power techniques, novel devices, circuits, and applications ---------------------------------------- Thu, Aug 26 AM (09:10 - 12:15) ---------------------------------------- (1) 09:10 - 09:35 On-Chip Supply Resonance Noise Reduction Method for Multi-IP Cores utilizing Parasitic Capacitance of Sleep Blocks Jinmyoung Kim, Toru Nakura (Univ. of Tokyo.), Hidehiro Takata, Koichiro Ishibashi (Renesas Electronics), Makoto Ikeda, Kunihiro Asada (Univ. of Tokyo.) (2) 09:35 - 10:00 An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa (Panasonic) (3) 10:00 - 10:25 An Over 20,000 Quality Factor On-Chip Relaxation Oscillator using Voltage Averaging Feedback with a Chopped Amplifier Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho (Panasonic Corp.) (4) 10:25 - 10:50 A 2.7mW 4th-Order Active Gm-RC Bandpass Filter with 60MHz Center Frequency and Digital/Analog Tuning Techniques Jingbo Shi, Takayuki Konishi, Toru Kashimura, Shoichi Masui (Tohoku Univ) ----- Break ( 10 min. ) ----- (5) 11:00 - 11:25 Investigation of Analog-to-Digital Converters using Time Dimension Masao Takayama, Takuji Miki, Shiro Dosho (Panasonic) (6) 11:25 - 11:50 10bit-300MHz Double-Sampling Pipelined ADC with Digital Calibration for Memory Effects Takuji Miki, Takashi Morie, Toshiaki Ozeki, Shiro Dosho (Panasonic) (7) 11:50 - 12:15 Pull-up/pull-down circuits with no static current consumption Tatsuya Ueno (Yamatake Corp.) ----- Lunch Break ( 45 min. ) ----- ---------------------------------------- Thu, Aug 26 PM (13:00 - 14:40) ---------------------------------------- (8) 13:00 - 13:25 1-Tbyte/s 1-Gbit 3-D DRAM Architecture for High Throughput Computing Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Tomonori Sekiguchi (Hitachi) (9) 13:25 - 13:50 Design Constraint of Fine Grain Supply Voltage Control LSI -- In the case of Power Gating Technique -- Atsuki Inoue (Fujitsu Lab. Ltd.) (10) 13:50 - 14:15 Design Constraint of Fine Grain Supply Voltage Control LSI -- In the case of DVFS Technique -- Atsuki Inoue (Fujitsu Lab. Ltd.) (11) 14:15 - 14:40 Power Analysis and Power Reduction Techniques of a 128GFLOPS/58W SPARC64VIIIfx Processor for Peta-scale Computing Yukihito Kawabe (Fujitsu Lab.), Hiroshi Okano, Ryuji Kan, Toshio Yoshida, Iwao Yamazaki, Hitoshi Sakurai, Mikio Hondou, Nobuyuki Matsui, Hideo Yamashita, Tatsumi Nakada, Takumi Maruyama, Takeo Asakawa (Fujitsu) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Aug 26 PM (14:50 - 19:00) ---------------------------------------- (12) 14:50 - 15:40 [Invited Talk] MEMS/BEANS-Enabled Green Technology Norihisa Miki (Keio Univ./BEANS Project) (13) 15:40 - 16:30 [Invited Talk] Development of MEMS Technologies for Micro Energy Systems Yuji Suzuki (Univ. of Tokyo.) (14) 16:30 - 17:20 [Invited Talk] A Wide-Area Sensor Network with Fiber Optic Power Supply Yosuke Tanaka, Takashi Kurokawa (Tokyo Univ. of A & T) ----- Break ( 10 min. ) ----- (15) 17:30 - 19:00 ---------------------------------------- Fri, Aug 27 AM (09:00 - 11:05) ---------------------------------------- (16) 09:00 - 09:25 Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement, Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs Shuhei Tanakamaru (Univ. of Tokyo), Atsushi Esumi, Mitsuyoshi Ito, Kai Li (SIGLEAD), Ken Takeuchi (Univ. of Tokyo) (17) 09:25 - 09:50 A 1.0V Power Supply, 9.5GByte/sec Write Speed, Single-Cell Self-Boost Program Scheme for Ferroelectric NAND Flash SSD Kousuke Miyaji, Shinji Noda, Teruyoshi Hatanaka (Univ. of Tokyo), Mitsue Takahashi, Shigeki Sakai (AIST), Ken Takeuchi (Univ. of Tokyo) (18) 09:50 - 10:15 A 60% Higher Write Speed, 4.2Gbps, 24-Channel 3D-Solid State Drive (SSD) with NAND Flash Channel Number Detector and Intelligent Program-Voltage Booster Teruyoshi Hatanaka, Koichi Ishida, Tadashi Yasufuku (Univ. of Tokyo), Shinji Miyamoto, Hiroto Nakai (Toshiba), Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi (Univ. of Tokyo) (19) 10:15 - 11:05 [Invited Talk] Development of sub-10um Thinning Technology using Actual Device Wafers Nobuhide Maeda, Kim Youngsuk (Univ. of Tokyo), Yukinobu Hikosaka, Takashi Eshita (FSL), Hideki Kitada, Koji Fujimoto (Univ. of Tokyo), Yoriko Mizushima (Fujitsu Labs.), Kousuke Suzuki (DNP), Tomoji Nakamura (Fujitsu Labs.), Akihito Kawai, Kazuhisa Arai (DISCO), Takayuki Ohba (Univ. of Tokyo) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Aug 27 AM (11:15 - 12:30) ---------------------------------------- (20) 11:15 - 11:40 Highly Scalable STT-MRAM with MTJs of Top-pinned Structure in 1T/1MTJ Cell Young Min Lee, Chikako Yoshida, Koji Tsunoda, Shinjiro Umehara, Masaki Aoki, Toshihiro Sugii (Fujitsu Labs, Ltd.) (21) 11:40 - 12:05 Study of stacked MRAM for universal memory Shouto Tamai, Shigeyoshi Watanabe (Shonan Inst. of Tech.) (22) 12:05 - 12:30 Study of stacked FeRAM using ITO channel Koichi Sugano, Shigeyoshi Watanabe (Shonan Inst. of Tech) ----- Lunch Break ( 50 min. ) ----- ---------------------------------------- Fri, Aug 27 PM (13:20 - 15:00) ---------------------------------------- (23) 13:20 - 13:45 Direct Measurement and Analysis of Static Noise Margin in SRAM Cells Using DMA TEG Toshiro Hiramoto, Makoto Suzuki, Takuya Saraya, Ken Shimizu (Univ. of Tokyo), Akio Nishida, Shiro Kamohara, Kiyoshi Takeuchi, Tohru Mogami (MIRAI-Selete) (24) 13:45 - 14:10 70% Read Margin Enhancement by VTH Mismatch Self-Repair in 6T-SRAM with Asymmetric Pass Gate Transistor by Zero Additional Cost, Post-Process, Local Electron Injection Kousuke Miyaji, Shuhei Tanakamaru, Kentaro Honda (Univ. of Tokyo), Shinji Miyano (STARC), Ken Takeuchi (Univ. of Tokyo) (25) 14:10 - 14:35 A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop Capable of Protecting Soft Errors on the C-element Jun Furuta (Kyoto Univ.), Chikara Hamanaka, Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Hidetoshi Onodera (Kyoto Univ.) (26) 14:35 - 15:00 Application of spin MOSFET to Nonvolatile and Reconfigurable LSIs Tomoaki Inokuchi, Takao Marukame, Tetsufumi Tanamoto, Hideyuki Sugiyama, Mizue Ishikawa, Yoshiaki Saito (Toshiba Corporation) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Aug 27 PM (15:10 - 16:50) ---------------------------------------- (27) 15:10 - 15:35 Circuit design of reconfigurable logic based on MOS double gate/Carbon Nano Tube transistor Takamichi Hayashi, Shigeyoshi Watanabe (Shonan Inst. of Tech.) (28) 15:35 - 16:00 Pattern Layout Methods of System LSI with SGT Takahiro Kodama, Shigeyoshi Watanabe (Shonan Inst. of Tech.) (29) 16:00 - 16:25 Random Drain Current Variation Caused by "Current-Onset Voltage" Variability in Scaled MOSFETs Tomoko Mizutani (Univ. of Tokyo), Takaaki Tsunomura (MIRAI-Selete), Anil Kumar (Univ. of Tokyo), Akio Nishida, Kiyoshi Takeuchi, Satoshi Inaba, Shiro Kamohara (MIRAI-Selete), Kazuo Terada (Hiroshima City Univ.), Tohru Mogami (MIRAI-Selete), Toshiro Hiramoto (Univ. of Tokyo/MIRAI-Selete) (30) 16:25 - 16:50 On the Gate-Stack Origin Threshold Voltage Variability in Scaled FinFETs and Multi-FinFETs Yongxun Liu, Kazuhiko Endo, Shinich Ouchi (AIST), Takahiro Kamei (Meiji Univ.), Junichi Tsukada, Hiromi Yamauchi, Yuki Ishikawa (AIST), Tetsuro Hayashida (Meiji Univ.), Kunihiro Sakamoto, Takashi Matsukawa (AIST), Atsushi Ogura (Meiji Univ.), Meishoku Masahara (AIST) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Silicon Device and Materials (SDM) === # FUTURE SCHEDULE: Thu, Oct 21, 2010 - Fri, Oct 22, 2010: Tohoku University [Wed, Aug 18], Topics: Semiconductor process science and new technology Thu, Nov 11, 2010 - Fri, Nov 12, 2010: Kikai-Shinko-Kaikan Bldg. [Fri, Sep 10], Topics: Process, Device, Circuit Simulations, etc # SECRETARY: Shigeru Kawanaka (Toshiba Corp.) Tel 045-776-5670 E-mail:  ge       ba === Technical Committee on Integrated Circuits and Devices (ICD) === # FUTURE SCHEDULE: Tue, Oct 5, 2010 - Wed, Oct 6, 2010: Makuhari Messe, International Conference Hall [Wed, Jul 21], Topics: Frontier of processor, DSP, and image processing supporting Digital Harmony Mon, Nov 22, 2010: Tokyo Tech Front [Thu, Sep 30], Topics: Technical Meeting on Silicon Analog RF Technologies Mon, Nov 29, 2010 - Wed, Dec 1, 2010: Kyushu University [Fri, Sep 10], Topics: Design Gaia 2010 ―New Field of VLSI Design― # SECRETARY: Hiroaki Suzuki (Renesas Electronics Corp.) TEL 072-787-2335 E-mail:   a   ub   s Last modified: 2010-06-22 17:43:35 |
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