Mon, Nov 6 AM
10:30 - 11:45 |
(1)
VLD |
10:30-10:55 |
hCODE 2.0: An Open-source Platform for FPGA Cluster System |
Hiroki Nakagawa, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
(2)
VLD |
10:55-11:20 |
Design Environment Construction for Three-Dimensional Sound Processor using High-Level Synthesis |
Saya Ohira, Naoki Tsuchiya, Tetsuya Matsumura (Nihon Univ.) |
(3)
VLD |
11:20-11:45 |
Considerations of Inside Structures for Approximate Multipliers |
Masahiro Inoue, Kaori Tajima, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) |
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11:45-13:00 |
Lunch Break ( 75 min. ) |
Mon, Nov 6 PM
13:00 - 13:45 |
(4)
ICD |
13:00-13:45 |
[Invited Talk]
Superconducting quantum computing |
Yasunobu Nakamura (UTokyo) |
Mon, Nov 6 PM
13:00 - 14:15 |
(5)
VLD |
13:00-13:25 |
Optimization of Cryptographic Hardware for Optimal Ate Pairing over BN Curves |
Tadayuki Ichihashi, Hiromitsu Awano, Makoto Ikeda (Tokyo Univ.) |
(6)
VLD |
13:25-13:50 |
Hardware Implementation of Elliptic Curve Cryptography for Sensor-Node Applications |
Ryosuke Saito, Hiromitsu Awano, Makoto Ikeda (The Univ. of Tokyo) |
(7)
DC |
13:50-14:15 |
An Evaluation for the Number of Decoding Key for Logic Encryption Methods for IP Cores |
Hashidate Hidemi, Hosokawa Toshinori (Nihon Univ.), Yoshimura Masayoshi (Kyoto Sangyo Univ.) |
Mon, Nov 6 PM
13:00 - 14:15 |
(8)
RECONF |
13:00-13:25 |
FPGA Implementation of Pattern Matching of PCRE for NIDS and its Acceleration and Memory Saving |
Masahiro Fukuda, Yasushi Inoguchi (JAIST) |
(9)
RECONF |
13:25-13:50 |
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(10)
RECONF |
13:50-14:15 |
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Ryo Kamasaka, Taisei Segawa, Yuichiro Shibata (Nagasaki Univ.) |
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14:15-14:30 |
Break ( 15 min. ) |
Mon, Nov 6 PM
14:30 - 15:45 |
(11)
VLD |
14:30-14:55 |
Reduction of Overhead in Adaptive Body Bias Technology due to Triple-well Structure |
Yasuhiro Ogasahara, Toshihiro Sekigawa, Hanpei Koike (AIST) |
(12)
VLD |
14:55-15:20 |
Leakage Energy Reduction for Digital Embedded Memory using Dynamic Multi Body Bias Control |
Yusuke Yoshida, Kimiyoshi Usami (SIT) |
(13)
VLD |
15:20-15:45 |
A shared memory chip for twin-tower of chips |
Sayaka Terashima, Takuya Kojima, Hayate Okuhara, Yusuke Matsushita, Naoki Ando (Keio Univ.), Mitaro Namiki (Tokyo Univ. of Agriculture and Tech.), Hideharu Amano (Keio Univ.) |
Mon, Nov 6 PM
14:30 - 15:45 |
(14)
DC |
14:30-14:55 |
A Method of LFSR Seed Generation for Improving Quality of Delay Fault BIST |
Kyonosuke Watanabe, Satoshi Ohtake (Oita Univ.) |
(15)
DC |
14:55-15:20 |
An Approach to Selection of Classifiers and their Thresholds for Machine Learning Based Fail Chip Prediction |
Daichi Yuruki, Satoshi Ohtake (Oita Univ), Yoshiyuki Nakamura (Renesas Electronics) |
(16)
DC |
15:20-15:45 |
A Test Register Assignment Method to Reduce the Number of Test Patterns at Register Transfer Level Using Controller Augmentation |
Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ), Masayoshi Yoshimura (Kyoto Sangyo Univ) |
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15:45-16:00 |
Break ( 15 min. ) |
Mon, Nov 6 PM
16:00 - 17:30 |
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Tue, Nov 7 AM
09:00 - 10:15 |
(17)
VLD |
09:00-09:25 |
Novel Implementation of FFT for Mixed Grained Reconfigurable Architecture Using Via-switch |
Tetsuaki Fujimoto (Ritsumeikan Univ.), Wataru Takahashi, Kazutoshi Wakabayashi (NEC), Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) |
(18)
VLD |
09:25-09:50 |
Routing method considering programming constraint of reconfigurable device using via-switch crossbars |
Kosei Yamaguchi, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) |
(19)
VLD |
09:50-10:15 |
A PUF Based on the Instantaneous Response of Ring Oscillator Determined by the Convergence Time of Bistable Ring Oscillator Circuit |
Yuki Tanaka, Song Bian, Masayuki Hiromoto, Takashi Sato (Kyoto Univ.) |
Tue, Nov 7 AM
09:00 - 10:15 |
(20)
DC |
09:00-09:25 |
Flip-Flop Selection for Multi-Cycle Test with Partial Observation in Scan-Based Logic BIST |
Shigeyuki Oshima, Takaaki Kato (Kyutech), Senling Wang (Ehime Univ.), Yasuo Sato, Seiji Kajihara (Kyutech) |
(21)
DC |
09:25-09:50 |
On Avoiding Test Data Corruption by Optimal Scan Chain Grouping |
Yucong Zhang, Stefan Holst, Xiaoqing Wen, Kohei Miyase, Seiji Kajihara (KIT), Jun Qian (AMD) |
(22)
VLD |
09:50-10:15 |
On low power oriented test pattern compaction using SAT solver |
Yusuke Matsunaga (Kyushu Univ.) |
Tue, Nov 7 AM
09:00 - 10:15 |
(23)
RECONF |
09:00-09:25 |
Real Chip Evaluation of a Variable Pipelined Coarse-Grained Reconfigurable Array |
Naoki Ando, Takuya Kojima, Hideharu Amano (Keio Univ.) |
(24)
RECONF |
09:25-09:50 |
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(25)
RECONF |
09:50-10:15 |
Performance Evaluation Three Dimensional FPGA Architecture with Face-down Stacking |
Keishiro Akashi, Motoki Amagasaki, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ) |
| |
10:15-10:30 |
Break ( 15 min. ) |
Tue, Nov 7 AM
10:30 - 11:45 |
(26)
VLD |
10:30-10:55 |
Area Reduction of Digital Circuit Part in Analog-to-Digital Converter Based on β-Expansion by Eliminating Look-Up Table |
Yuji Shindo, Kenshu Seto, Hao San (TCU) |
(27)
VLD |
10:55-11:20 |
A Study of Pipelined Hardware Design of Matrix Inversion for Signal Separation in MIMO-OFDM Wireless Communication |
Takashi Imagawa (Ritsumeikan Univ.), Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga (Hokkaido Univ.) |
(28)
VLD |
11:20-11:45 |
Implementation and Optimization of Parallel Prefix Adder Using Majority Function |
Daiki Matsumoto, Masao Yanagisawa, Shinji Kimura (Waseda Univ.) |
Tue, Nov 7 AM
10:30 - 11:45 |
(29)
VLD |
10:30-10:55 |
Stochastic Number Generation with Internal Signals of Peripheral Logic Circuits |
Naoya Kubota, Maki Fujiha, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) |
(30)
VLD |
10:55-11:20 |
Stochastic logic circuit using static constant as coefficient without random number generator |
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(31)
DC |
11:20-11:45 |
Design to Improve Open Defect Detection for Test Based on IDDT Appearance Time |
Ayumu Kambara, Kouhei Ohtani, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.) |
Tue, Nov 7 AM
10:30 - 11:45 |
(32)
RECONF |
10:30-10:55 |
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(33)
RECONF |
10:55-11:20 |
|
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(34)
RECONF |
11:20-11:45 |
IoT Platform using an MCU-FPGA Hybrid System and Feasibility Study of Wireless Configuration |
Ryota Suzuki, Hironori Nakajo (TUAT) |
| |
11:45-13:00 |
Lunch Break ( 75 min. ) |
Tue, Nov 7 PM
13:00 - 13:45 |
(35)
VLD |
13:00-13:45 |
[Invited Talk]
Innovative Applications of Machine Learning in Lithography and DFM |
Tetsuaki Matsunawa (Toshiba Memory) |
Tue, Nov 7 PM
13:00 - 14:15 |
(36)
ICD |
13:00-13:25 |
A Low-Voltage Operation Self-Calibration Hysteresis Comparator |
Takumi Saito, Satoshi Komatsu (TDU) |
(37)
ICD |
13:25-13:50 |
Real chip evaluation of a low-power overhead body bias controller |
Hayate Okuhara, Akram BenAhmed, Hideharu Amano (Keio Univ.) |
(38)
ICD |
13:50-14:15 |
Low Voltage Operation Boost Converter for ReRAM/NAND Flash Memory Hybrid SSD |
Kenta Suzuki, Kota Tsurumi, Ken Takeuchi (Chuo Univ.) |
Tue, Nov 7 PM
13:00 - 14:15 |
(39)
RECONF |
13:00-13:25 |
Calculation method of exponential function on FPGAs using high-radix STL method |
Yasufumi Fujiwara, Kazuyoshi Takagi, Naofumi Takagi (Kyoto Univ.) |
(40)
RECONF |
13:25-13:50 |
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(41)
RECONF |
13:50-14:15 |
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| |
14:15-14:30 |
Break ( 15 min. ) |
Tue, Nov 7 PM
14:00 - 15:15 |
(42)
VLD |
14:00-14:25 |
* |
Tomotaka Inoue, Kento Hasegawa (Waseda Univ.), Yuki Kobayashi (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(43)
VLD |
14:25-14:50 |
* |
Kento Hasegawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(44)
DC |
14:50-15:15 |
A Detection Method for Trojan Circuit inserted in Manufacturing Process |
Yoshinobu Okuda, Masayoshi Yoshimura, Kohei Ohyama (Kyoto Sangyo Univ.) |
Tue, Nov 7 PM
14:30 - 15:45 |
(45)
ICD |
14:30-14:55 |
Design of Weak-Signal-Readout-System for Terahertz-Video-Imaging |
Toshiyuki Kikkawa, Makoto Ikeda (The Univ. of Tokyo) |
(46)
ICD |
14:55-15:20 |
Simulation Techniques for EMC Compliant Design of Automotive IC Chips and Modules |
Akihiro Tsukioka, Makoto Nagata, Kohki Taniguchi, Daisuke Fujimoto (Kobe Univ.), Rieko Akimoto, Takao Egami, Kenji Niinomi, Takeshi Yuhara, Sachio Hayashi (TOSHIBA), Rob Mathews, Karthik Srinivasan, Ying-Shiun Li, Norman Chang (ANSYS) |
(47)
ICD |
15:20-15:45 |
Prospects of an Error-Correction Technique of Intra-Chip Data Transmission Using Time-Series Feature |
Kentaro Kato, Masanori Natsui, Takahiro Hanyu (Tohoku Univ.) |
Tue, Nov 7 PM
14:30 - 15:45 |
(48)
CPSY |
14:30-14:55 |
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(49)
CPSY |
14:55-15:20 |
DCNN Training with Short Bit Length Format Considering Loss of Trailing Digits |
Shin-ichi O'uchi, Hiroshi Fuketa, Ryousei Takano (AIST) |
| (50) |
15:20-15:45 |
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15:45-16:00 |
Break ( 15 min. ) |
Tue, Nov 7 PM
15:30 - 16:45 |
| (51) |
15:30-15:55 |
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| (52) |
15:55-16:20 |
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| (53) |
16:20-16:45 |
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Tue, Nov 7 PM
16:00 - 16:45 |
(54)
ICD |
16:00-16:45 |
[Invited Talk]
Researchs on high-speed and efficient Deep Learning technologies |
Takuya Fukagai, Koichi Shirahata, Yasumoto Tomita, Tetsutaro Hashimoto, Atsushi Ike, Masafumi Yamazaki, Akihiko Kasagi, Tsuguchika Tabaru (Fujitsu Lab. Ltd.), Liuan Wang, Song Wang, Li Sun, Jun Sun (FRDC) |
Tue, Nov 7 PM
16:00 - 16:45 |
(55)
CPSY |
16:00-16:45 |
[Invited Talk]
Application of Real-time Image Recognition System with Machine and Transfer Learnings to Computer-Aided Diagnosis for Endoscopic Images of Colorectal Cancer |
Tetsushi Koide, Toru Tamaki (Hiroshima Univ.), Shigeto Yoshida, Hiroshi Mieno (Medical Corp. JR Hiroshima Hospital), Shinji Tanaka (Hiroshima Univ. Hospital) |
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16:45-17:00 |
Break ( 15 min. ) |
Tue, Nov 7 PM
17:00 - 17:50 |
| (56) |
17:00-17:50 |
[Keynote Address]
Theory and applications of dynamical sparse modeling |
Masaaki Nagahara (Univ. of Kitakyushu) |
Tue, Nov 7 PM
18:30 - 20:30 |
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Wed, Nov 8 AM
09:00 - 10:15 |
(57)
CPSY |
09:00-09:25 |
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| (58) |
09:25-09:50 |
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| (59) |
09:50-10:15 |
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Wed, Nov 8 AM
09:00 - 10:15 |
(60)
VLD |
09:00-09:25 |
A Packet Lookup Engine LSI with Automatic Rule Registration and Deletion Function |
Yoshifumi Kawamura, Kousuke Imamura (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.), Yoshio Matsuda (Kanazawa Univ.) |
(61)
VLD |
09:25-09:50 |
Real-time coefficient optimization method for PAM-4 transmitter equalizer |
Yosuke Iijima, Keigo Taya (NIT, Oyama college), Yasushi Yuminaka (Gunma Univ.) |
(62)
VLD |
09:50-10:15 |
A General Model of Timing Correction by Temperature Dependent Clock Skew |
Mineo Kaneko (JAIST) |
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10:15-10:30 |
Break ( 15 min. ) |
Wed, Nov 8 AM
10:30 - 11:30 |
| (63) |
10:30-11:30 |
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11:30-12:30 |
Lunch Break ( 60 min. ) |
Wed, Nov 8 PM
12:30 - 13:45 |
| (64) |
12:30-12:55 |
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(65)
CPSY |
12:55-13:20 |
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(66)
CPSY |
13:20-13:45 |
Analysis of Data Access Locality from Redis KVS Database |
Hiroyuki Baba, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) |
Wed, Nov 8 PM
12:45 - 13:45 |
(67)
IE |
12:45-13:45 |
[Invited Talk]
Accurate Color Reproduction using Multiband Image and Its Applications |
Masaru Tsuchida, Kaoru Hiramatsu, Kunio Kashino (NTT) |
Wed, Nov 8 PM
12:30 - 13:45 |
(68)
DC |
12:30-12:55 |
Application of blind watermarking method for secondary use on smart community |
Yuta Ohno, Akira Niwa, Hiroaki Nishi (Keio Univ.) |
| (69) |
12:55-13:20 |
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| (70) |
13:20-13:45 |
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13:45-14:00 |
Break ( 15 min. ) |
Wed, Nov 8 PM
14:00 - 15:15 |
(71)
CPSY |
14:00-14:25 |
Accelerating Blockchain Search using GPU |
Shin Morishima, Hiroki Matsutani (Keio Univ.) |
(72)
CPSY |
14:25-14:50 |
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(73)
CPSY |
14:50-15:15 |
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Wed, Nov 8 PM
14:00 - 15:15 |
(74)
IE |
14:00-14:25 |
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(75)
IE |
14:25-14:50 |
Pixel-Wise Exposure Controllable Column Parallel Readout Image Sensor and HDR Image Reconstruction |
Takuro Kosaka, Takayuki Hamamoto (TUS) |
(76)
IE |
14:50-15:15 |
Global Shutter CMOS Image Sensor with Correlated Multiple Sampling Architecture |
Hiroyuki Yamaguchi, Toshinori Otaka, Yotaro Imai, Takayuki Hamamoto (TUS) |
Wed, Nov 8 PM
14:00 - 15:15 |
| (77) |
14:00-14:25 |
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| (78) |
14:25-14:50 |
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| (79) |
14:50-15:15 |
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15:15-15:30 |
Break ( 15 min. ) |
Wed, Nov 8 PM
15:30 - 16:45 |
| (80) |
15:30-15:55 |
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| (81) |
15:55-16:45 |
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Wed, Nov 8 PM
15:30 - 16:45 |
(82)
VLD |
15:30-15:55 |
A Study on Target Pin-Pairs Selection for Set-Pair Routing |
Kano Akagi, Shimpei Sato, Atsushi Takahashi (Tokyo Tech.) |
(83)
VLD |
15:55-16:20 |
Max Length and Length Difference Minimization for Set Pair Routing Problem with ILP |
Shutaro Hara, Kunihiro Fujiyoshi (TUAT) |
(84)
VLD |
16:20-16:45 |
An Efficient Search Method on Stacked Rectangular Dissections |
Masaki Yokota, Kunihiro Fujiyoshi (TUAT) |
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