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Technical Committee on Dependable Computing (DC) [schedule] [select]
Chair Tomohiro Yoneda (NII)
Vice Chair Seiji Kajihara (Kyushu Inst. of Tech.)
Secretary Masato Kitagami (Chiba Univ.), Michinobu Nakao (Renesas)

Conference Date Fri, Jun 25, 2010 13:30 - 16:45
Topics  
Conference Place Kikai-Shinko-Kaikan 
Transportation Guide http://www.jspmi.or.jp/mapright.htm

Fri, Jun 25 PM 
13:30 - 15:00
(1) 13:30-14:00 A Full Scan Design Method for Asynchronous Sequential Circuits Based on C-element Scan Paths Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara (NAIST)
(2) 14:00-14:30 A Class of Partial Thru Testable Sequential Circuits with Multiplexers Nobuya Oka, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
(3) 14:30-15:00 A Binding Algorithm in High-Level Synthesis for Robust Testable Datapaths Yuki Yoshikawa, Shun Maruya, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.)
  15:00-15:15 Break ( 15 min. )
Fri, Jun 25 PM 
15:15 - 16:45
(4) 15:15-15:45 A test pattern matching method on BAST architecture using don't care identification for the detection of random pattern resistant faults Yun Chen, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyushu Univ.)
(5) 15:45-16:15 Note on Insertion Point and Area of Observation Circuit for On-Chip Debug Technique Masayuki Arai, Yoshihiro Tabata, Kazuhiko Iwasaki (Tokyo Metro. Univ.)
(6) 16:15-16:45 An I/O Sequence Slicing Method for Post-silicon Debugging Yeonbok Lee, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo.)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 10 minutes for discussion.

Contact Address and Latest Schedule Information
DC Technical Committee on Dependable Computing (DC)   [Latest Schedule]
Contact Address Masato Kitakami
Graduate School of Advanced Integration Science,
Chiba University
1-33 Yayoi-cho Inage-ku, Chiba 263-8522 JAPAN
TEL/FAX +43.290.3039
E--mail:fultyba-u 


Last modified: 2010-04-17 00:47:06


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