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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Masato Motomura (Hokkaido Univ.)
Vice Chair: Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (Tohoku Univ.)
Secretary: Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant: Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)

DATE:
Mon, Sep 25, 2017 10:30 - 17:30
Tue, Sep 26, 2017 10:00 - 14:45

PLACE:
(東銀座駅（日比谷線, 浅草線）5番出口より徒歩3分. https://www.doorkeeper.jp/%E4%BC%9A%E5%A0%B4/dwango. Takayoshi Katsumata)

TOPICS:
Reconfigurable Systems, etc.

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Mon, Sep 25 AM (10:30 - 11:20)
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(1) 10:30 - 10:55
Pattern-matching-based game strategies and the strategy difference in pattern sizes
Masataka Nakano, Yoshiki Yamaguchi (Univ. of Tsukuba)

(2) 10:55 - 11:20
A thorough investigation of FPGA performance for PCIe Gen3 communication
Hiroki Nakamura, Hirotaka Takayama, Yoshiki Yamaguchi, Taisuke Boku (Univ. of Tsukuba)

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Mon, Sep 25 PM (13:30 - 14:45)
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(3) 13:30 - 13:55
(See Japanese page.)

(4) 13:55 - 14:20
A Study of Applicability of FPGA Dynamic Partial Reconfiguration Technique on COTS-based Carrier Network Equipment with HW/SW Co-design Scheme
Toru Homemoto, Hisaharu Ishii, Toshiya Matsuda, Masaru Katayama, Kazuyuki Matsumura (NTT)

(5) 14:20 - 14:45
A Memory Reduction with Neuron Pruning for a Binarized Deep Convolutional Neural Network: Its FPGA Realization
Tomoya Fujii, Shimpei Sato, Hiroki Nakahara (Tokyo Inst. of Tech.)

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Mon, Sep 25 PM (15:00 - 16:15)
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(6) 15:00 - 15:25
Hardware acceleration for holographic memories on optically reconfigurable gate arrays
Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)

(7) 15:25 - 15:50
Proplsal of reconfigurable system LSI with BiCS technology
-- Application to combination logic, FF, CMOS circuit and FPGA --
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shouto Tamai (Oi Electric), Takumi Sato (Japan Business Systems)

(8) 15:50 - 16:15
Performance analysis of Mono-Instruction Set Computer using VTR
Hiroki Shinba, Minoru Watanabe (Shizuoka Univ.)

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Mon, Sep 25 PM (16:30 - 17:30)
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(9) 16:30 - 17:30
[Invited Talk]
Scalable and convertible FPGA DNN accelerator
Shinichi Suto, Takato Yamada (LeapMind)

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Tue, Sep 26 AM (10:00 - 10:50)
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(10) 10:00 - 10:25
GUINNESS: A GUI based Binarized Deep Neural Network Framework for an FPGA
Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato (Tokyo Inst. of Tech.)

(11) 10:25 - 10:50
High-speed Calculation of k-means Clustering Using FPGA and its Application to Pick and Place Machine
Shogo Nakamura, Hiroki Ebara, Kenji Kanazawa (Univ. of Tsukuba), Noriyuki Aibe (Keio Univ.), Moritoshi Yasunaga (Univ. of Tsukuba)

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Tue, Sep 26 AM (11:00 - 12:00)
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(12) 11:00 - 12:00
[Invited Talk]
Increasing Productivity Using Xilinx Development Tools
Louie Valena (Xilinx)

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Tue, Sep 26 PM (13:30 - 14:45)
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(13) 13:30 - 13:55
(See Japanese page.)

(14) 13:55 - 14:20
A case study of High-level Synthesis Using Higher-order Function on Functional Language
Takuya Teraoka, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

(15) 14:20 - 14:45
Implementing RISC-V with a Python-Based High-Level Synthesis Compiler
Ryouzaburo Suzuki, Hiroaki Kataoka (Sinby)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:

Mon, Nov 6, 2017 - Wed, Nov 8, 2017: Kumamoto-Kenminkouryukan Parea [Mon, Sep 11], Topics: Design Gaia 2017 -New Field of VLSI Design-

# SECRETARY:
Inquiries for RECONF
Masato Motomura (Hokkaido Univ.) :