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Technical Committee on VLSI Design Technologies (VLD) [schedule] [select]
Chair Hiroyuki Ochi (Ritsumeikan Univ.)
Vice Chair Noriyuki Minegishi (Mitsubishi Electric)
Secretary Shinobu Nagayama (Hiroshima City Univ.), Koyo Nitta (NTT)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [schedule] [select]
Chair Yutaka Tamiya (Fujitsu Laboratories)
Secretary Seiya Shibata (NEC), Yukio Mitsuyama (Kochi Univ. of Tech.), Eiichi Hosoya (NTT)

Conference Date Wed, May 16, 2018 13:30 - 16:15
Topics System Design, etc. 
Conference Place  
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Wed, May 16 PM 
13:30 - 14:45
13:30-13:55 Partial logic synthesis by using sum of products or product of sums based quantified boolean formulae VLD2018-1 Xiaoran Han, Amir Masoud Gharehbaghi, Masahiro Fujita (UTokyo)
(2) 13:55-14:20  
(3) 14:20-14:45  
  14:45-15:00 Break ( 15 min. )
Wed, May 16 PM 
15:00 - 16:15
15:00-15:25 Non-volatile Power Gating for Data Cache with Dynamic Line-selection VLD2018-2 Sosuke Akiba, Kimiyoshi Usami (SIT)
(5) 15:25-15:50  
15:50-16:15 Pixel-based OPC using Quadratic Programming for Mask Optimization VLD2018-3 Rina Azuma, Yukihide Kohira (Univ. of Aizu)

Announcement for Speakers
General TalkEach speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
VLD Technical Committee on VLSI Design Technologies (VLD)   [Latest Schedule]
Contact Address Shinobu Nagayama (Hiroshima City University)
E-: s_-cu 
Announcement See also VLD's homepage:
IPSJ-SLDM Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)   [Latest Schedule]
Contact Address Yukio Mitsuyama (Kochi Univ. of Tech.)
Announcement Please see the IPSJ-SLDM page below:

Last modified: 2018-10-21 19:33:59

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