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Technical Committee on VLSI Design Technologies (VLD)
Chair: Atsushi Takahashi (Osaka Univ.) Vice Chair: Ikuo Harada (NTT)
Secretary: Nozomu Togawa (Waseda Univ.), Akihisa Yamada (Sharp)

DATE:
Thu, Sep 24, 2009 13:30 - 17:30
Fri, Sep 25, 2009 10:00 - 14:35

PLACE:
110, Bldg A, Graduate School of Infomation Science and Technology, Osaka Univeristy(1-5 Yamadaoka, Suita, Osaka 565-0871, Japan. http://www.ist.osaka-u.ac.jp/japanese/access/index.html. Prof. Masanori Hashimoto. +81-6-6879-4526)

TOPICS:
Physical design, etc

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Thu, Sep 24 PM Physical Design Technology (13:30 - 14:45)
Chair: Daisuke Fukuda (Fujitsu Lab.)
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(1) 13:30 - 13:55
Fast Global Floorplanning Method Based on Stable-LSE
Yasuhiro Takashima, Masatomo Kuwano (Univ. of Kitakyushu)

(2) 13:55 - 14:20
A Detail Via Arrangement Method for Reduction of Wire Congestion in 2-Layer Ball Grid Array Packages
Masaki Kinoshita, Yoichi Tomioka (Tokyo Inst. of Tech.), Atsushi Takahashi (Osaka Univ.)

(3) 14:20 - 14:45
A Wall Generation for Trunk Routing of Multiple Nets on Single Layer
Yukihide Kohira (Univ. of Aizu.), Atsushi Takahashi (Osaka Univ.)

----- Break ( 15 min. ) -----

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Thu, Sep 24 PM System and Logic Design Technology (15:00 - 16:15)
Chair: Nozomu Togawa (Waseda Univ.)
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(4) 15:00 - 15:25
Complete ILP-Formulation of High-Level Synthesis
Keisuke Inoue, Mineo Kaneko (JAIST)

(5) 15:25 - 15:50
A System LSI Design and Verification Environment Using JACKAL Language
Takafumi Kohara (Kinki Univ.), Ryuichi Nakawaki (FUJITSU FSAS), Yasuhiro Nagata (NEC System Techno.), Takashi Kambe (Kinki Univ.)

(6) 15:50 - 16:15
On accelleration of SER analysis for sequential circuits using implicit enumeration
Yusuke Matsunaga, Yusuke Akamine (Kyushu Univ.)

----- Break ( 15 min. ) -----

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Thu, Sep 24 PM Invited Talks (16:30 - 17:30)
Chair: Atsushi Takahashi (Osaka Univ.)
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(7) 16:30 - 17:30
[Invited Talk]
Trace-Driven Workload Simulation Method for Multiprocessor System-On-Chips
Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda (Tokyo Inst. of Tech.), Toshiro Isomura, Kazuo Satou (TOYOTA MOTOR CORP.)

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Fri, Sep 25 AM System Design (10:00 - 10:50)
Chair: Akihisa Yamada (Sharp)
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(8) 10:00 - 10:25
An Approach for Algorithm Tuning of Power Grid Simulation by GPGPU
Makoto Yokota, Yuuya Isoda, Hisako Sugano, Ittetsu Taniguchi, Masahiro Fukui (Ritsumeikan Univ.)

(9) 10:25 - 10:50
Triage Device Slightly Injured Person in Disaster Medical Assistant Network
Keishi Sakanushi, Akihito Hiromori (Osaka Univ/JST), Taichiro Imamura, Junya Okamoto (Osaka Univ), Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ/JST), Junji Kitamichi (Osaka Univ), Teruo Higashino (Osaka Univ/JST)

----- Break ( 15 min. ) -----

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Fri, Sep 25 AM Reconfigurable Systems I (11:05 - 11:55)
Chair: Akihisa Yamada (Sharp)
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(10) 11:05 - 11:30
High Throughput Irregular LDPC Decoder Based on High-Efficiency Column Operation Unit for IEEE 802.11n Standard
Akiyuki Nagashima, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.)

(11) 11:30 - 11:55
DFG Mapping for Flexible Engine/Generic ALU Array and Its Dedicated Synthesis Algorithm
Ryo Tamura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Makoto Satoh (Hitachi Ltd.)

----- Lunch Break ( 85 min. ) -----

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Fri, Sep 25 PM Reconfigurable Systems II (13:20 - 14:35)
Chair: Ikuo Harada (NTT)
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(12) 13:20 - 13:45
A remote optically reconfigurable gate array using fibers
Yumiko Ueno, Minoru Watanabe (Shizuoka Univ.)

(13) 13:45 - 14:10
A configuration speed acceleration method using negative logic implementation
Retsu Moriwaki, Minoru Watanabe (Shizuoka Univ.)

(14) 14:10 - 14:35
Defect tolerance of a MEMS dynamic optically reconfigurable gate array
Daisaku Seto, Minoru Watanabe (Shizuoka Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

# CONFERENCE SPONSORS:
- Co-sponsored by the IEEE CAS Society Kansai Chapter

=== Technical Committee on VLSI Design Technologies (VLD) ===
# FUTURE SCHEDULE:

Wed, Dec 2, 2009 - Fri, Dec 4, 2009: Kochi City Culture-Plaza [Mon, Sep 14], Topics: Design Gaia 2009 ―New Field of VLSI Design―

# SECRETARY:
Nozomu Togawa (Waseda Univ.)
E-mail: n