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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Kimiyoshi Usami (Shibaura Inst. of Tech.) Vice Chair: Akihisa Yamada (Sharp) Secretary: Kazutoshi Kobayashi (Kyoto Inst. of Tech.), Takashi Takenaka (NEC) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Michiaki Muraoka (Kochi Univ.) Secretary: Hiroaki Komatsu (Fujitsu), Naoki Iwata (Sony), Nozomu Togawa (Waseda Univ.) DATE: Wed, May 30, 2012 14:30 - 17:20 Thu, May 31, 2012 09:30 - 11:45 PLACE: Kitakyushu International Conference Center(http://www.convention-a.jp/access/. Prof. Shigetoshi Nakatake. +81-93-695-3268) TOPICS: System Design, etc. ---------------------------------------- Wed, May 30 PM System Design (14:30 - 16:10) Chair: Hiroshi Saito (Univ. of Aizu) ---------------------------------------- (1)/VLD 14:30 - 14:55 Task Allocation Optimization Method Using SA Method to Automatically Set Starting Temperature for Multi-Processor System Yuichiro Yanabu, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) (2)/VLD 14:55 - 15:20 Multiple supply voltages aware high-speed and high-efficient high-level synthesis for HDR architectures Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) (3)/VLD 15:20 - 15:45 Write Control Method Based on State Transition for Magnetic Flip-Flop Naoya Okada (Waseda Univ.), Yuichi Nakamura (NEC), Shinji Kimura (Waseda Univ.) (4)/VLD 15:45 - 16:10 High-level Design Debugging Using Potential Dependence Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) ----- Break ( 10 min. ) ----- ---------------------------------------- Wed, May 30 PM Invited Talk (16:20 - 17:20) Chair: Kimiyoshi Usami (Shibaura Inst. Tech.) ---------------------------------------- (5) 16:20 - 17:20 [Invited Talk] How to Mitigate Reliability-related Issues on Nano-scaled LSIs Kazutoshi Kobayashi (KIT) ---------------------------------------- Thu, May 31 AM Physical Design (09:30 - 10:45) Chair: Yukihide Kohira (Univ. of Aizu) ---------------------------------------- (6)/VLD 09:30 - 09:55 Sub-path delay estimation for reconvergent path Seiya Nagatsuka, Yasuhiro Takashima (Univ. of Kitakyushu) (7)/VLD 09:55 - 10:20 A Placement Method on Overlapped Printed-Wiring-Boards Tetsuya Matsuura, Kunihiro Fujiyoshi (TUAT) (8)/VLD 10:20 - 10:45 A Comparator Energy Model Considering Shallow Trench Isolation by Geometric Programming Gong Chen, Yu Zhang, Bo Yang, Qing Dong, Shigetoshi Nakatake (Kitakyushu Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 31 AM Design Environment (10:55 - 11:45) Chair: Yasuhiro Takashima (Univ. of Kitakyushu) ---------------------------------------- (9)/VLD 10:55 - 11:20 Development of an FPGA Design Support Tool Set for Asynchronous Circuits with Bundled-data Implementation Keitaro Takizawa, Minoru Iizuka, Hiroshi Saito (Univ. of Aizu) (10)/VLD 11:20 - 11:45 Statistical Analysis and its Hardware Implementation on Simulation Results of Systems with Uncertain Inputs Kosuke Oshima, Shohei Ono, Takeshi Matsumoto, Masahiro Fujita (Univ. of Tokyo) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Mon, Jul 2, 2012 - Tue, Jul 3, 2012: Kyoto Research Park [Thu, Apr 26] # SECRETARY: Kazutoshi Kobayashi (Kyoto Institute of Technology) E-mail:       ba   t Tel: +81-75-724-7452 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # SECRETARY: Nozomu Togawa (Waseda University) Email sldm2012 g    # ANNOUNCEMENT: # See also SLDM homepage: http://www.sig-sldm.org/ Last modified: 2012-05-14 15:18:30 |
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