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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Minoru Watanabe (Shizuoka Univ.)
Vice Chair: Masato Motomura (Hokkaido Univ.), Yuichiro Shibata (Nagasaki Univ.)
Secretary: Yoshiki Yamaguchi (Univ. of Tsukuba), Kazuya Tanigawa (Hiroshima City Univ.)
Assistant: Takefumi Miyoshi (e-trees.Japan), Yuuki Kobayashi (NEC)

DATE:
Mon, Sep 5, 2016 13:10 - 17:25
Tue, Sep 6, 2016 09:10 - 14:40

PLACE:
Toyama University(e-trees.Japan, Inc, Takefumi MIYOSHI)

TOPICS:
Reconfigurable Systems, etc.

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Mon, Sep 5 PM Applications (1) (13:10 - 14:25)
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(1) 13:10 - 13:35
Functional Improvement of cReComp Design Tool for Software-Component Generation of FPGA Processing
Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.)

(2) 13:35 - 14:00
(See Japanese page.)

(3) 14:00 - 14:25
[Short Paper]
Study and Evaluation of FPGA based I/O Accelerator for the Flash Storage
Kazushi Nakagawa, Shotaro Shintani, Hirotoshi Akaike, Kentaro Shimada (Hitachi)

----- Break ( 10 min. ) -----

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Mon, Sep 5 PM High Level Synthesis (14:35 - 15:25)
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(4) 14:35 - 15:00
The effect of the C ++ template meta-programming in high-level synthesis
Kenichiro Mitsuda, Owada Hiroshi, Shinji Yamamoto (ISP)

(5) 15:00 - 15:25
(See Japanese page.)

----- Break ( 10 min. ) -----

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Mon, Sep 5 PM Place and Route (15:35 - 16:25)
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(6) 15:35 - 16:00
Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shoto Tamai (Oi Electric), Takumi Sato (Shonan Inst. of Tech.)

(7) 16:00 - 16:25

Tomohiro Tanaka, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (Taiyo Yuden)

----- Break ( 10 min. ) -----

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Mon, Sep 5 PM Invited Talk (1) (16:35 - 17:25)
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(8) 16:35 - 17:25
[Invited Talk]
Verification and Debugging Support Techniques for High-Level Designs
Takeshi Matsumoto (INCT)

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Tue, Sep 6 AM Invited Talk (2) (09:10 - 10:00)
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(9) 09:10 - 10:00
[Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC)

----- Break ( 30 min. ) -----

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Tue, Sep 6 AM Platform (10:30 - 11:45)
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(10) 10:30 - 10:55
Concept of PC-FPGA Hybrid Cluster system by General-purpose FPGA board
Keisuke Takano, Akira Uejima, Ryo Ozaki, Masaki Kohata (Okayama Univ. of Science)

(11) 10:55 - 11:20
A Study of Methodology and Tools for Open-source FPGA Accelerators
Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(12) 11:20 - 11:45
(See Japanese page.)

----- Break ( 75 min. ) -----

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Tue, Sep 6 PM Applications (2) (13:00 - 14:40)
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(13) 13:00 - 13:25
A Memory-based Accelerator for a Random Forest Classification using Altera SDK for OpenCL
Hiroki Nakahara, Akira Jinguji, Tomoya Fujii, Shinpei Sato (TITECH), Naoya Maruyama (RIKEN)

(14) 13:25 - 13:50
A Memory Based Realization of the Binarized Deep Convolutional Neural Network
Hiroki Nakahara, Haruyoshi Yonekawa (TITECH), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (Poco a poco Networks), Masato Motomura (Hokkaido Univ.)

(15) 13:50 - 14:15
An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation
Daichi Murata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.)

(16) 14:15 - 14:40
(See Japanese page.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:

Mon, Nov 28, 2016 - Wed, Nov 30, 2016: Ritsumeikan University, Osaka Ibaraki Campus [Sun, Sep 11], Topics: Design Gaia 2016 -New Field of VLSI Design-

# SECRETARY:
Inquiries for RECONF
Minoru Watanabe (Shizuoka University)
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