Mon, Sep 5 PM Applications (1)
13:10 - 14:25 |
| (1) |
13:10-13:35 |
Functional Improvement of cReComp Design Tool for Software-Component Generation of FPGA Processing |
Kazushi Yamashina, Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota (Utsunomiya Univ.) |
| (2) |
13:35-14:00 |
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| (3) |
14:00-14:25 |
[Short Paper]
Study and Evaluation of FPGA based I/O Accelerator for the Flash Storage |
Kazushi Nakagawa, Shotaro Shintani, Hirotoshi Akaike, Kentaro Shimada (Hitachi) |
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14:25-14:35 |
Break ( 10 min. ) |
Mon, Sep 5 PM High Level Synthesis
14:35 - 15:25 |
| (4) |
14:35-15:00 |
The effect of the C ++ template meta-programming in high-level synthesis |
Kenichiro Mitsuda, Owada Hiroshi, Shinji Yamamoto (ISP) |
| (5) |
15:00-15:25 |
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15:25-15:35 |
Break ( 10 min. ) |
Mon, Sep 5 PM Place and Route
15:35 - 16:25 |
| (6) |
15:35-16:00 |
Proposal of vertical stacked reconfigurable Fe-FET NAND logic and its application to combination logic, flip-flop and LUT |
Shigeyoshi Watanabe (Shonan Inst. of Tech.), Tomohiro Yokota (DNP Data Techno), Shoto Tamai (Oi Electric), Takumi Sato (Shonan Inst. of Tech.) |
| (7) |
16:00-16:25 |
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Tomohiro Tanaka, Kazuya Tanigawa, Tetsuo Hironaka (Hiroshima City Univ), Takashi Ishiguro (Taiyo Yuden) |
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16:25-16:35 |
Break ( 10 min. ) |
Mon, Sep 5 PM Invited Talk (1)
16:35 - 17:25 |
| (8) |
16:35-17:25 |
[Invited Talk]
Verification and Debugging Support Techniques for High-Level Designs |
Takeshi Matsumoto (INCT) |
Tue, Sep 6 AM Invited Talk (2)
09:10 - 10:00 |
| (9) |
09:10-10:00 |
[Invited Talk]
Accelerating an IoT Application by using CPU-FPGA tightly coupled architecture |
Yuki Kobayashi, Yoshikazu Watanabe, Seiya Shibata, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura (NEC) |
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10:00-10:30 |
Break ( 30 min. ) |
Tue, Sep 6 AM Platform
10:30 - 11:45 |
| (10) |
10:30-10:55 |
Concept of PC-FPGA Hybrid Cluster system by General-purpose FPGA board |
Keisuke Takano, Akira Uejima, Ryo Ozaki, Masaki Kohata (Okayama Univ. of Science) |
| (11) |
10:55-11:20 |
A Study of Methodology and Tools for Open-source FPGA Accelerators |
Takuya Nakamichi, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
| (12) |
11:20-11:45 |
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11:45-13:00 |
Break ( 75 min. ) |
Tue, Sep 6 PM Applications (2)
13:00 - 14:40 |
| (13) |
13:00-13:25 |
A Memory-based Accelerator for a Random Forest Classification using Altera SDK for OpenCL |
Hiroki Nakahara, Akira Jinguji, Tomoya Fujii, Shinpei Sato (TITECH), Naoya Maruyama (RIKEN) |
| (14) |
13:25-13:50 |
A Memory Based Realization of the Binarized Deep Convolutional Neural Network |
Hiroki Nakahara, Haruyoshi Yonekawa (TITECH), Tsutomu Sasao (Meiji Univ.), Hisashi Iwamoto (Poco a poco Networks), Masato Motomura (Hokkaido Univ.) |
| (15) |
13:50-14:15 |
An Efficient and Small-Scaled RNN Hardware Architecture Based on Approximation of RNN Algorithm for Hardware Implementation |
Daichi Murata, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa (Kobe Univ.) |
| (16) |
14:15-14:40 |
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