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Technical Committee on Superconductive Electronics (SCE)
Chair: Akira Fujimaki (Nagoya Univ.)
Secretary: Hiroyuki Akaike (Nagoya Univ.), Hiroyuki Shibata (NTT)
Assistant: Hiroaki Myoren (Saitama Univ.)

DATE:
Thu, Jul 22, 2010 09:30 - 14:55

PLACE:
Kikaishinkou-kaikan(3-5-8, Shibakouen, Minato-ku, Tokyo, 105-0011 Japan.10 minutes walk from Kamiya-cho station of Metro Hibiya-line. https://www.ieice.org/jpn/about/syozai.html. Nagoya Univ. Hiroyuki Akaike. +81-52-789-3324)

TOPICS:
Signal processing technologies and their applications, etc.

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Thu, Jul 22 AM (09:30 - 12:00)
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(1) 09:30 - 09:55
Design of semi-synchronous error correction circuit for superconducting flash type ADC
Kazumasa Ishihara (Tokyo Denki Univ./ISTEC), Hideo Suzuki (ISTEC), Kazunori Miyahara (Tokyo Denki Univ.), Mutsuo Hidaka (ISTEC)

(2) 09:55 - 10:20
High-Speed Operation of Single Flux Quantum Logic Up/Down Counter for Digital DROS
Kosuke Terui, Yun Kimimoto, Tohru Taino, Hiroaki Myoren (Saitama Univ.)

(3) 10:20 - 10:45
An Integrated Cryogenic Current Comparator
Michitaka Maruyama, Chiharu Urano, Takehiko Oe, Masaaki Maezawa, Takahiro Yamada (AIST), Mutsuo Hidaka, Tetsuro Satoh, Shuichi Nagasawa, Kenji Hinode (ISTEC), Nobu-hisa Kaneko (AIST)

(4) 10:45 - 11:10
High-Speed Test of a Radix-2 Butterfly Processing Element for the Fast Fourier Transform using SFQ Circuits
Fumishige Miyaoka, Toshiki Kainuma, Yasuhiro Shimamura, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.)

(5) 11:10 - 11:35
Development of circuit design and evaluation environments for superconductor devices
Takahiro Yamada, Masaaki Maezawa, Satoshi Kohjiro (AIST)

(6) 11:35 - 12:00
Fault Modeling and Test Generation for Single Flux Quantum Logic Circuits
Nobutaka Kito (Kyoto Univ.), Masamitsu Tanaka, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.)

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Thu, Jul 22 PM (13:15 - 14:55)
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(7) 13:15 - 13:40
Investigation to Speed Up Single-flux-quantum Circuits by Applying Higher Bias Voltage
Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi (Nagoya Univ./JST), Nobuyuki Yoshikawa (Yokohama National Univ./JST), Shuichi Nagasawa (SRL/JST), Naofumi Takagi (Kyoto Univ./JST)

(8) 13:40 - 14:05
Demonstration of a 4x4 SFQ switch fabricated with the ISTEC 10-kA/cm2 Nb Advanced process 2
Masato Ito, Irina Kataeva, Masakazu Okada, Tomohito Kouketsu, Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.)

(9) 14:05 - 14:30
50 GHz Tests of SFQ Floating-Point Multipliers Using 10 kA/cm2 Nb Advanced Process
Yasuhiro Shimamura, Toshiki Kainuma, Fumishige Miyaoka, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Akira Fujimaki, Kazuyoshi Takagi (Nagoya Univ.), Naofumi Takagi (Kyoto Univ.)

(10) 14:30 - 14:55
Operations of Single Flux Quantum Circuits Based on 40-kA/cm^2 Process
Tomohito Kouketsu, Hiroyuki Akaike, Akira Fujimaki (Nagoya Univ.), Tetsuro Satoh, Kenji Hinode, Shuichi Nagasawa, Mutsuo Hidaka (SRL)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on Superconductive Electronics (SCE) ===
# FUTURE SCHEDULE:

Tue, Oct 19, 2010: Kikai-Shinko-Kaikan Bldg. [Thu, Aug 19], Topics: Fundamental Technologies for Superconducting Electronics, etc.

# SECRETARY:
Hiroyuki Akaike (Nagoya Univ.)
TEL: +81-52-789-3324, FAX: +81-52-789-3160
email: a