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=============================================== Technical Committee on Superconductive Electronics (SCE) Chair: Keiichi Tanabe (ISTEC) Secretary: Takashi Uchida (National Defense Academy), Tsunehiro Hatou (ISTEC) Assistant: Hiroaki Myoren (Saitama Univ.), Masaaki Maezawa (AIST) DATE: Thu, Oct 30, 2008 09:30 - 17:10 PLACE: AIST Tsukuba Central 2, 8F AV room-1(1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan. Take a train (rapid service, 45 min. or semi-rapid service, 52min.) from Akihabara Station and get off at Tsukuba Station (next to the Tsukuba Center bus terminal). Take exit A4 for public transportation or exit A3 for AIST shuttle bus. Take the Kanto Tetsudo bus going to “Arakawaoki Station (West Entrance) via Namiki” or “Ami Chuo Kominkan” from platform #4 at Tsukuba Center Bus Terminal. Get off at “Namiki 2-chome (namiki nì-chomé)” . Walk 3 minutes to AIST Tsukuba Central.http://www.aist.go.jp/aist_e/guidemap/tsukuba/tsukuba_map.html. AIST Hiroshi Sato, ISTEC-SRL Mutsuo Hidaka. 029-861-5022) TOPICS: Present status and future prospects for single flux quantum LSI technology, Digital application, etc ---------------------------------------- Thu, Oct 30 AM (09:30 - 12:45) ---------------------------------------- (1) 09:30 - 09:35 Introductory talk Keiichi Tanabe (ISTEC-SRL) (2) 09:35 - 10:20 [Invited Talk] REGQ Technologies for Very High End Computing John Spargo (Northrop Grumman Space Technology) (3) 10:20 - 10:55 [Invited Talk] SFQ Technology Developments in NEDO Next-Generation High-Efficiency Network Device project Mutsuo Hidaka (SRL) (4) 10:55 - 11:30 [Invited Talk] JST and MEXT SFQ Device Projects -- For New Innovation of SFQ Electronics -- Akira Fujimaki (Nagoya Univ.) ----- Break ( 15 min. ) ----- (5) 11:45 - 12:45 Panel discussion ---------------------------------------- Thu, Oct 30 PM (14:00 - 17:10) ---------------------------------------- (6) 14:00 - 14:25 Design of SFQ circuits using logic cells directly connectable to PTLs Hidetoshi Suzuki, Hiroshi Hara, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ) (7) 14:25 - 14:50 Mutual Inductance between Two Superconducting Lines Parallely-Placed in Nb Integrated Circuits Akio Kawai, Ryuta Kashiwa, Masataka Moriya, Tadayuki Kobayashi, Yoshinao Mizugaki (UEC) (8) 14:50 - 15:15 Demonstration of a Single-Flux-Quantum Floating-Point Divider for the Reconfigurable Data-path Masamitsu Tanaka, Koji Obata, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.), Nobuyuki Yoshikawa (Yokohama National Univ.) (9) 15:15 - 15:40 Design and test of memory system in the SFQ-FFT processor Kazuhiro Taketomi, Yuki Yamanashi, Heejoung Park, Nobuyuki Yoshikawa (YNU) ----- Break ( 15 min. ) ----- (10) 15:55 - 16:20 Automated Routing Method for Multi-Layer SFQ Circuits Shota Takeshima, Masamitsu Tanaka, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ.) (11) 16:20 - 16:45 Investigation of Inductively Coupled SFQ Pulse Transfer Circuits for Current Recycling Masanori Igarashi, Yuki Yamanashi, Nobuyuki Yoshikawa (Yokohama National Univ.), Kan Fujiwara, Yoshihito Hashimoto (SRL) (12) 16:45 - 17:10 Research on effective moat configuration for Nb multi-layer device structure for a cell library Kan Fujiwara, Shuichi Nagasawa, Mutsuo Hidaka (SRL/CREST-JST), Nobuyuki Yoshikawa (Yokohama National Univ./CREST-JST), Masamitsu Tanaka, Hiroyuki Akaike, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi (Nagoya Univ./CREST-JST) # Information for speakers Invited Talk (45/35分) will have 40/30 minutes for presentation and 5 minutes for discussion. General Talk (25分) will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Superconductive Electronics (SCE) === # FUTURE SCHEDULE: Thu, Jan 29, 2009: Kikai-Shinko-Kaikan Bldg [Sun, Nov 16], Topics: Analog application, etc # SECRETARY: Takashi Uchida (NDA) TEL: 046-841-3810, FAX: 046-844-5903 email: u    n Last modified: 2008-08-21 20:35:10 |
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