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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Toshinori Sueyoshi Vice Chair: Akira Nagoya, Tomomi Sato
Secretary: Tetsuo Hironaka, Yuichiro Shibata
Assistant: Masahiro Iida

DATE:
Thu, May 17, 2007 13:00 - 17:50
Fri, May 18, 2007 09:00 - 11:40

PLACE:

TOPICS:
Reconfigurable Systems, etc.

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Thu, May 17 PM (13:00 - 15:00)
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(1) 13:00 - 13:30
Query-Transaction Accelaration Appliance with a DRP using Stateful Packet-by-Packet Self-Reconfiguration
Takashi Isobe (Hitachi)

(2) 13:30 - 14:00
An implementation of template matching algorithm using levenshtein distance on FPGA
Souichi Shimizu, Takamasa Kanamori (Keio Univ.), Yoshiaki Ajioka (Ecchandes), Masatoshi Arai, Daisuke Konno, Nanba Tomoyasu (Calsonic Kansei), Hideharu Amano (Keio Univ.)

(3) 14:00 - 14:30
Autometic combining of rate law functions for an FPGA-based biochemical simulator ReCSiP
Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata (Nagasaki Univ.), Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi (Keio Univ.), Noriko Hiroi (EMBL-EBI), Hiroaki Kitano (JST), Kiyoshi Oguri (Nagasaki Univ.)

(4) 14:30 - 15:00
*
Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)

----- Break ( 10 min. ) -----

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Thu, May 17 PM (15:10 - 17:50)
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(5) 15:10 - 15:40
3-D Dynamically Reconfiguarable Device using Inter-Chip Wireless Communication MuCCRA-Cube
Shotaro Saito, Yohei Hasegawa, Yoshinori Kohama, Yasufumi Sugimori, Hideharu Amano (Keio Univ.)

(6) 15:40 - 16:10
<Subject Undecided>
Masaharu Yoneda, Masaru Fukushi, Susumu Horiguchi (Tohoku Univ.)

(7) 16:10 - 16:40
Performance Evaluation of Variable Grain Logic Cell for Arithmetic Circuits
Yoshiaki Satou, Motoki Amagasaki, Ryoichi Yamaguchi, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

----- Break ( 10 min. ) -----

(8) 16:50 - 17:20
Detailed Evaluation of Delay for the Small-World Network Routing Structure
Yuzo Nishioka (Kumamoto Univ.), Hisashi Tsukiashi (Renesas Technology), Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

(9) 17:20 - 17:50
A Discussion on a Router for embedded Programmable Logic matriX (ePLX)
Naoki Okuno, Tomonori Izumi, Takeshi Fujino (Ritsumeikan Univ.), Takenobu Iwao, Hirofumi Nakano, Yoshihiro Okuno, Kazutami Arimoto (Renesas)

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Fri, May 18 AM (09:00 - 11:40)
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(10) 09:00 - 09:30
Techniques to decrease the Configuration Data Transfer Time in Dynamically Reconfigurable Processor MuCCRA
Toru Sano, Takuro Nakamura, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano (Keio Univ)

(11) 09:30 - 10:00
Power Reduction of Dynamical Reconfigurable Processor MuCCRA
Keiichiro Hirai (Keio Univ.), Seidai Takeda (SIT.), Takashi Nishimura, Youhei Hasegawa, Satoshi Tsutsumi (Keio Univ.), Kimiyoshi Usami (SIT.), Hideharu Amano (Keio Univ.)

(12) 10:00 - 10:30
MuCCRA-D:A Dynamically Reconfigurable Processor with Directly Interconnected PEs
Masaru Kato, Yohei Hasegawa, Hideharu Amano (Keio Univ.)

----- Break ( 10 min. ) -----

(13) 10:40 - 11:10
A Study of the Dynamic Reconfigurable Processor Vulcan2 and Its Development Tool ISAcc
Tetsuo Hiraki, Shingo Kadouchi, Yosuke Yamazaki (Kyushu Univ.), Takayuki Kando, Lovic Gauthier, Victor Goulart Mauro Ferreira (FLEETS), Antoine Trouve (ISIT), Koji Inoue, Kazuaki Murakami (Kyushu Univ.)

(14) 11:10 - 11:40
*
Hiroshi Kadota (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.)

=== Technical Committee on Reconfigurable Systems (RECONF) ===

# SECRETARY:
Masahiro IIDA (Kumamoto Univ.)
E-mail: ii