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=============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Kentaro Sano (RIKEN) Vice Chair: Yoshiki Yamaguchi (Tsukuba Univ.), Tomonori Izumi (Ritsumeikan Univ.) Secretary: Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.) Assistant: Yukitaka Takemura (INTEL), Yasunori Osana (Ryukyu Univ.) DATE: Fri, Sep 10, 2021 09:30 - 16:35 PLACE: (Yukitaka Takemura, Intel) TOPICS: Reconfigurable system, etc. ---------------------------------------- Fri, Sep 10 AM AI Application (09:30 - 10:45) ---------------------------------------- (1) 09:30 - 09:55 A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech) (2) 09:55 - 10:20 An FPGA Implementation of neural networks with multi-core structured using high level synthesis Akira Jinguji, Hiroki Nakahara (Tokyo Tech) (3) 10:20 - 10:45 Convolutional neural network implementations using Vitis AI Akihiko Ushiroyama, Nobuya Watanabe, Akira Nagoya, Minoru Watanabe (Okayama Univ.) ----- Break ( 15 min. ) ----- ----- Lunch break (RECONF Research Committee meeting will be held.) ( 105 min. ) ----- ---------------------------------------- Fri, Sep 10 PM (12:45 - 13:00) ---------------------------------------- (4) 12:45 - 13:00 ---------------------------------------- Fri, Sep 10 PM Invited Talk (13:00 - 13:50) ---------------------------------------- (5) 13:00 - 13:50 [Invited Talk] Development of a very high-speed, low power computer system for Deep Learning at Preferred Networks Kei Hiraki (PFN) ----- Break ( 20 min. ) ----- ---------------------------------------- Fri, Sep 10 PM FPGA Application 1 (14:10 - 15:25) ---------------------------------------- (6) 14:10 - 14:35 (See Japanese page.) (7) 14:35 - 15:00 (See Japanese page.) (8) 15:00 - 15:25 Parallel Calculation of Local Scores in Bayesian Network Structure Learning using FPGA Ryota Miyagi (Kyoto Univ.), Hideki Takase (U. Tokyo/JST) ----- Break ( 20 min. ) ----- ---------------------------------------- Fri, Sep 10 PM FPGA Application 2 (15:45 - 16:35) ---------------------------------------- (9) 15:45 - 16:10 (See Japanese page.) (10) 16:10 - 16:35 Multi-FPGA Based Hardware Acceleration for Genetic Data Analysis Imdad Ullah (Keio Univ.), Akram Ben Ahmed (AIST), Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Reconfigurable Systems (RECONF) === # FUTURE SCHEDULE: Wed, Dec 1, 2021 - Thu, Dec 2, 2021: Online [Fri, Sep 3], Topics: Design Gaia 2021 -New Field of VLSI Design- # SECRETARY: Yukitaka Takemura (Intel) E-mail:          in l Tomonori Izumi (Ritsumeikan Univ.) E-mail: t-i       i # ANNOUNCEMENT: # http://www.ieice.org/~reconf/ https://join.slack.com/t/reconfworkspace/shared_invite/zt-v3qeynk3-RsInu4wdjqU2t_ysqWvagg Last modified: 2021-09-10 09:40:11 |
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