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Technical Committee on Dependable Computing (DC)
Chair: Nobuyasu Kanekawa (Hitachi) Vice Chair: Michiko Inoue (NAIST)
Secretary: Koji Iwata (RTRI), Masayoshi Yoshimura (Kyoto Sangyo Univ.)
DATE:
Wed, Feb 17, 2016 10:00 - 16:30
PLACE:
(3-5-8, Shiba-Koen, Minato-ku, Tokyo, 105-0111 Japan.http://www.jspmi.or.jp/kaigishitsu/access.html)
TOPICS:
VLSI Design and Test, etc.
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Wed, Feb 17 AM (10:00 - 11:15)
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(1) 10:00 - 10:25
Note on Simultaneous Multiple Transient Fault Detection Based on Dual Approximate Logic
Keisuke Sonehara, Masayuki Arai (Nihon Univ.)
(2) 10:25 - 10:50
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation
Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech)
(3) 10:50 - 11:15
Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value
Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
----- Break ( 15 min. ) -----
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Wed, Feb 17 AM (11:30 - 12:20)
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(4) 11:30 - 11:55
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences
Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.)
(5) 11:55 - 12:20
Delay fault injection framework based on logic simulation with zero delay model
Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST)
----- Lunch Break ( 100 min. ) -----
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Wed, Feb 17 PM (14:00 - 15:15)
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(6) 14:00 - 14:25
A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis
Hideyuki Takano, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Koji Yamazaki (Meiji Univ.)
(7) 14:25 - 14:50
Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding
Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST)
(8) 14:50 - 15:15
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns
Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU)
----- Break -----
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Wed, Feb 17 PM (15:15 - 16:30)
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(9) 15:15 - 15:40
Analog Circuit Design for a Precision Resistance Measurement of TSVs
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.)
(10) 15:40 - 16:05
The Hybrid Communication Protocol for CANs
Koji Konomi, Muneyuki Nakamura, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.)
(11) 16:05 - 16:30
Study on the Effect of Power Supply Noise on Flip-Flop Circuits
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.)
# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.
=== Technical Committee on Dependable Computing (DC) ===
# FUTURE SCHEDULE:
Thu, Mar 24, 2016 - Fri, Mar 25, 2016: Fukue Bunka Hall/Rodou Fukushi Center [Wed, Jan 13], Topics: ETNET2016
Mon, May 9, 2016 - Tue, May 10, 2016: Unaduki Suginoi Hotel [Fri, Mar 11], Topics: Dependable Computing Systems, etc. (HotSPA: Hot SPring Annual meeting)
Mon, May 16, 2016 - Tue, May 17, 2016: Institute of Industrial Science, University of Tokyo [unfixed], Topics: LSI and System Workshop 2016
Last modified: 2015-12-23 20:40:52
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