Wed, May 11 AM 10:00 - 11:40 |
(1) VLD |
10:00-10:25 |
An Application of Subgradient Method to Delay Analysis |
Hiroshi Miyashita, Koutaro Kawaraguchi (The Univ. of Kitakyushu) |
(2) VLD |
10:25-10:50 |
Self-Aligned Double Patterning-Aware Two-color Grid Routing |
Hatsuhiko Miura, Mitsuru Hasegawa, Taku Hirukawa, Kunihiro Fujiyoshi (TUAT) |
(3) |
10:50-11:15 |
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(4) |
11:15-11:40 |
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11:40-13:00 |
Lunch Break ( 80 min. ) |
Wed, May 11 PM 13:00 - 14:15 |
(5) |
13:00-13:25 |
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(6) |
13:25-13:50 |
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(7) VLD |
13:50-14:15 |
Multi bit soft error tolerant FPGA architecture |
Yuji Nakamura, Takuya Teraoka, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) |
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14:15-14:30 |
Break ( 15 min. ) |
Wed, May 11 PM 14:30 - 15:45 |
(8) VLD |
14:30-14:55 |
A High-Level Synthesis Algorithm using Critical Path Optimization Based Operation Chainings for RDR Architectures |
Kotaro Terada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) |
(9) VLD |
14:55-15:20 |
A Note on Scheduling Problem Considering the Radiation Resistance of Registers |
Keisuke Inoue (KTC), Mineo Kaneko (JAIST) |
(10) VLD |
15:20-15:45 |
MERP-CNN: A Memory-Efficient Reconfigurable Processor for Convolutional Neural Networks Based on FPGA |
Xushen Han, Dajiang Zhou, Shinji Kimura (Waseda Univ.) |
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15:45-16:00 |
Break ( 15 min. ) |
Wed, May 11 PM 16:00 - 17:00 |
(11) VLD |
16:00-17:00 |
[Invited Talk]
Challenges of DA Technologies for the Future
-- For the Establishment of Next Generation DA Technologies -- |
Michiaki Muraoka (Kochi Univ.) |