Mon, Jan 25 AM HPC 09:00 - 10:40 |
(1) CPSY |
09:00-09:25 |
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(2) RECONF |
09:25-09:50 |
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(3) RECONF |
09:50-10:15 |
Study on Design and Evaluation of Stream Processing Hardware for Sound Simulation by FDTD method |
Hiroki Tada (JAIST), Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano (R-CCS), Ryuta Kawano, Yasushi Inoguchi (JAIST) |
(4) RECONF |
10:15-10:40 |
An implementation and evaluation of Fast Fourier Transform on FPGA for High-performance Computing |
Takaaki Miyajima, Tomohiro Ueno, Kentaro Sano (RIKEN) |
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10:40-10:55 |
Break ( 15 min. ) |
Mon, Jan 25 AM 10:55 - 11:55 |
(5) CPSY |
10:55-11:55 |
[Invited Talk]
System Architecture and Interconnect Development for the Supercomputer "K" and "Fugaku" |
Yuichiro Ajima (Fujitsu) |
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11:55-12:55 |
Break ( 60 min. ) |
Mon, Jan 25 PM 12:55 - 14:10 |
(6) CPSY |
12:55-13:20 |
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(7) CPSY |
13:20-13:45 |
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(8) CPSY |
13:45-14:10 |
Throughput improvement of Responsive Link with High Speed Transceiver in FPGA |
Masahiko Takahashi, Yamasaki Nobuyuki (Keio Univ.) |
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14:10-14:25 |
Break ( 15 min. ) |
Mon, Jan 25 PM 14:25 - 16:05 |
(9) CPSY |
14:25-14:50 |
Evaluations of FPGA-based Neural Networks using of ODE |
Hirohisa Watanabe, Hiroki Matsutani (Keio Univ.) |
(10) RECONF |
14:50-15:15 |
Efficient Attention Mechanism by Softmax Function with Trained Coefficient |
Kaito Hirota (UT), O'uchi Shinichi (AIST), Fujita Masahiro (UT) |
(11) RECONF |
15:15-15:40 |
A High-speed Convolutional Neural Network Accelerator for an Adaptive Resolution on an FPGA |
Koki Sayama, Akira Jinguji, Naoto Soga, Hiroki Nakahara (Tokyo Tech) |
(12) RECONF |
15:40-16:05 |
Implementation of Quantized Deep Neural Network on FPGA |
Pan Hongyi (AIST/The Univ. of Tokyo), Ben Ahmed Akram, Ikegami Tsutomu (AIST), Tominaga Kazuki (The Univ. of Tokyo), Kudoh Tomohiro (AIST/The Univ. of Tokyo) |
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16:05-16:20 |
Break ( 15 min. ) |
Mon, Jan 25 PM 16:20 - 18:00 |
(13) VLD |
16:20-16:45 |
Residual signed-digit number - residual binary number conversion algorithm |
Yuki Saba, Yuuki Tanaka, Shugang Wei (Gunma Univ.) |
(14) VLD |
16:45-17:10 |
Comparison of ICA Algorithms in the Compressed Sensing EEG Measurement Framework Using OD-ICA |
Wataru Okumura, Daisuke Kanemoto, Osamu Maida, Tetsuya Hirose (Osaka Univ) |
(15) VLD |
17:10-17:35 |
Low Power EEG Measurement Using Compressed Sensing Consideration of the Sampling Interval |
Yuki Okabe, Daisuke Kanemoto (Osaka Univ.), Tomoya Mochizuki (Yamanashi Univ.), Osamu Maida, Tetsuya Hirose (Osaka Univ.) |
(16) VLD |
17:35-18:00 |
High speed architectures of decimal counters |
Shuhei Yanagawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.) |
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18:00-18:30 |
Break ( 30 min. ) |
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18:30-20:30 |
Social Event ( 120 min. ) |
Tue, Jan 26 AM 09:00 - 10:15 |
(17) CPSY |
09:00-09:25 |
Acceleration of Database Query Processing Using FPGA |
Hirohiko Ozaku (UEC), Masato Yoshimi (TIS), Celimuge Wu, Tsutomu Yoshinaga (UEC) |
(18) RECONF |
09:25-09:50 |
FPGA Accelerator Design for Real-Time Object Detection |
Koichiro Ban, Masanori Furuta, Daisuke Kobayashi (Toshiba) |
(19) RECONF |
09:50-10:15 |
FPGA Implementation of Semantic Segmentation on LWIR Images for Autonomous Robot |
Yuichiro Niwa (ATLA), Taiki Fujii (eSOL) |
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10:15-10:30 |
Break ( 15 min. ) |
Tue, Jan 26 AM 10:30 - 11:45 |
(20) CPSY |
10:30-10:55 |
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(21) CPSY |
10:55-11:20 |
Network Intrusion Detection System based on Hybrid FPGA/GPU Pattern Matching |
Shunta Kikuchi (AIST/The Univ. of Tokyo), Tsutomu Ikegami, Akram ben Ahmed (AIST), Tomohiro Kudoh (The Univ. of Tokyo/AIST), Ryohei Kobayashi, Norihisa Fujita, Taisuke Boku (Univ. of Tsukuba) |
(22) RECONF |
11:20-11:45 |
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Hiroaki Suzuki (Keio Univ), Wataru Takahashi (NEC), Kazutoshi Wakabayashi (Tokyo Univ), Hideharu Amano (Keio Univ) |
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11:45-12:45 |
Break ( 60 min. ) |
Tue, Jan 26 PM 12:45 - 14:00 |
(23) RECONF |
12:45-13:10 |
SLM based FPGA-IP soft core |
Yuya Nakazato, Hiroaki Koga (Kumamoto Univ.), Zhao Qian (KIT), Motoki Amagasaki, Morihiro Kuga, Masahiro Iida (Kumamoto Univ.) |
(24) RECONF |
13:10-13:35 |
Automated architecture exploration on Scala-based hardware development environment |
Ryota Yamashita, Daichi Teruya, Hironori Nakajo (TUAT) |
(25) |
13:35-14:00 |
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14:00-14:15 |
Break ( 15 min. ) |
Tue, Jan 26 PM 14:15 - 15:55 |
(26) VLD |
14:15-14:40 |
A new method for evaluating corruption metric and resilience of logic locking |
Shusaku Minami, Yusuke Matsunaga (Kyushu Univ.) |
(27) VLD |
14:40-15:05 |
Mutation-Based Fuzzing Using Data Structure Captured via Data Generator |
Noriyuki Namba, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(28) VLD |
15:05-15:30 |
Detection of Vulnerability Inducing Code Optimization Based on Binary Code |
Yuka Azuma, Nagisa Ishiura (Kwansei Gakuin Univ.) |
(29) VLD |
15:30-15:55 |
Performance Testing of VRP Optimization of C Compilers by Random Program Generation |
Daiki Murakami, Nagisa Ishiura (Kwansei Gakuin Univ.) |
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15:55-16:10 |
Break ( 15 min. ) |
Tue, Jan 26 PM 16:10 - 17:25 |
(30) |
16:10-16:35 |
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(31) |
16:35-17:00 |
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(32) |
17:00-17:25 |
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