Wed, Feb 17 AM 10:00 - 11:15 |
(1) |
10:00-10:25 |
Note on Simultaneous Multiple Transient Fault Detection Based on Dual Approximate Logic |
Keisuke Sonehara, Masayuki Arai (Nihon Univ.) |
(2) |
10:25-10:50 |
Logic-Path-and-Clock-Path-Aware At-Speed Scan Test Generation |
Fuqiang Li, Xiaoqing Wen, Stefan Holst, Kohei Miyase, Seiji Kajihara (Kyutech) |
(3) |
10:50-11:15 |
Reduction of open fault test pattern generation time by selection of adjacent lines for assigning logic value |
Kazui Fujitnai, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
|
11:15-11:30 |
Break ( 15 min. ) |
Wed, Feb 17 AM 11:30 - 12:20 |
(4) |
11:30-11:55 |
Acceleration of Stochastic Computing by Dynamically Sharing Consecutive Bit Sequences |
Kensuke Takamori, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) |
(5) |
11:55-12:20 |
Delay fault injection framework based on logic simulation with zero delay model |
Shinji Kawasaki, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) |
|
12:20-14:00 |
Lunch Break ( 100 min. ) |
Wed, Feb 17 PM 14:00 - 15:15 |
(6) |
14:00-14:25 |
A Ranking Method of Suspicious Candidate Faults Using Fault Excitation Condition Analysis for Universal Logical Fault Diagnosis |
Hideyuki Takano, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon Univ.), Koji Yamazaki (Meiji Univ.) |
(7) |
14:25-14:50 |
Built-In Self-Test with Combination of Weighted Random Pattern and Reseeding |
Sayaka Satonaka, Tomokazu Yoneda, Yuta Yamato, Michiko Inoue (NAIST) |
(8) |
14:50-15:15 |
An RTL Test Point Insertion Method to Reduce the Number of Test Patterns |
Naoya Ohsaki, Toshinori Hosokawa, Hiroshi Yamazaki (NU), Masayoshi Yoshimura (KSU) |
|
- |
Break |
Wed, Feb 17 PM 15:15 - 16:30 |
(9) |
15:15-15:40 |
Analog Circuit Design for a Precision Resistance Measurement of TSVs |
Senling Wang, Keisuke Kagawa (Ehime Univ.), Shuichi Kameyama (Fujitsu), Yoshinobu Higami, Hiroshi Takahashi (Ehime Univ.) |
(10) |
15:40-16:05 |
The Hybrid Communication Protocol for CANs |
Koji Konomi, Muneyuki Nakamura, Kazuya Sakai, Satoshi Fukumoto (Tokyo Metropolitan Univ.) |
(11) |
16:05-16:30 |
Study on the Effect of Power Supply Noise on Flip-Flop Circuits |
Takuya Yamamoto, Yukiya Miura (Tokyo Metropolitan Univ.) |