IEICE Technical Report

Online edition: ISSN 2432-6380

Reconfigurable Systems

Workshop Date : 2021-09-10 / Issue Date : 2021-09-03

RECONF2021-17
A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA
Ryosuke Kuramochi, Hiroki Nakahara (Tokyo Tech)
pp. 1 - 6

RECONF2021-18
An FPGA Implementation of neural networks with multi-core structured using high level synthesis
Akira Jinguji, Hiroki Nakahara (Tokyo Tech)
pp. 7 - 12

RECONF2021-19
Convolutional neural network implementations using Vitis AI
Akihiko Ushiroyama, Nobuya Watanabe, Akira Nagoya, Minoru Watanabe (Okayama Univ.)
pp. 13 - 18

RECONF2021-20
(See Japanese page.)
pp. 19 - 23

RECONF2021-21
(See Japanese page.)
pp. 24 - 29

RECONF2021-22
Parallel Calculation of Local Scores in Bayesian Network Structure Learning using FPGA
Ryota Miyagi (Kyoto Univ.), Hideki Takase (U. Tokyo/JST)
pp. 30 - 35

RECONF2021-23
(See Japanese page.)
pp. 36 - 41

RECONF2021-24
Multi-FPGA Based Hardware Acceleration for Genetic Data Analysis
Imdad Ullah (Keio Univ.), Akram Ben Ahmed (AIST), Kazuei Hironaka, Kensuke Iizuka, Hideharu Amano (Keio Univ.)
pp. 42 - 47

Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.

The Institute of Electronics, Information and Communication Engineers (IEICE), Japan