Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2016-70
A Hardware Acceleration of Template Matching using FPGA and MPU
Yuji Matumoto, Youichi Tomioka, Junji Kitamichi (The University of Aizu)
pp. 1 - 6
VLD2016-71
Optimal Design of FIR filter using a Real Coded Genetic Algorithm Processor
Akihiko Tsukahara, Akinori Kanasugi (Tokyo Denki Univ.)
pp. 7 - 12
VLD2016-72
GRAPE9-MPX: development of an accelerator system dedicated for multi-precision arithmetic operations and its application
Hiroshi Daisaka (Hitotsubashi Univ.), Naohito Nakasato (Univ. of Aizu), Tadashi Ishikawa, Fukuko Yuasa (KEK), Keigo Nitadori (RIKEN/AICS)
pp. 13 - 18
VLD2016-73
(See Japanese page.)
pp. 19 - 23
VLD2016-74
(See Japanese page.)
pp. 25 - 29
VLD2016-75
Implementation of Multiple FPGAs with High Speed Serial Optical Interconnection
Futoshi Murase, Daichi Takagi, Motoki Amagasaki, Morihiro Kuga, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ)
pp. 31 - 36
VLD2016-76
Distributed Handshake-Join Processing for Stream Data on Multiple FPGA Nodes
Kousuke Tada, Naoto Kawahara, Masato Yoshimi, Celimuge, Wu., Tsutomu Yoshinaga (UEC)
pp. 37 - 42
VLD2016-77
A Case for FPGA Based 10GbE Switch Aggregating Computation Results of GPUs
Kazuma Takemoto, Ami Hayashi, Shin Morishima, Hiroki Matsutani (Keio Univ.)
pp. 43 - 48
VLD2016-78
(See Japanese page.)
pp. 49 - 54
VLD2016-79
A Memory Reduction with Neuron Pruning for a Convolutional Neural Network: Its FPGA Realization
Tomoya Fujii, Simpei Sato, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido univ.)
pp. 55 - 60
VLD2016-80
Overview of an HLS Framework Surpporting IoT/CPS Development
Daichi Teruya, Hironori Nakajo (TUAT)
pp. 61 - 66
VLD2016-81
Framework for a Hybrid System with a pair of MCU and FPGA
Ryota Suzuki, Nakajo Hironori (TUAT)
pp. 67 - 72
VLD2016-82
A Case for Remote GPU Assignment for VR Applications
Shin Morishima, Masahiro Okazaki (Keio Univ.), Hiroki Matsutani (Keio Univ.PRESTO/NII)
pp. 85 - 90
VLD2016-83
Evaluation of the PEACH3 used for communication in application
Takahiro Kaneda (Keio Univ.), Toshihiro Hanawa (UTokyo), Hideharu Amano (Keio Univ.)
pp. 91 - 96
VLD2016-84
Optimization of Fresnel hologram computation on GPU using decomposition method
Shinpei Watanabe (Utsunomiya Univ.), Boaz Jessie Jackin (NICT), Takeshi Ohkawa, Kanemitsu Ootsu, Takashi Yokota, Yoshio Hayasaki, Toyohiko Yatagai, Takanobu Baba (Utsunomiya Univ.)
pp. 97 - 102
VLD2016-85
Implementation of Path Profiler Using Loop Block for Dynamic Behavior Analysis of Nested Loops
Yuki Kikuchi, Kanemitsu Ootsu, Takanobu Baba, Takashi Yokota, Takeshi Ohkawa (Utsunomiya Univ.)
pp. 103 - 108
VLD2016-86
Expression of Positional registers for Tamper resistance
Kiyohiro Sato, Naoki Fujieda, Shuichi Ichikawa (TUT)
pp. 109 - 114
VLD2016-87
Proposal of Processor Enabling to Start-Up Internal Modules Distributed Energy Consumption
Hiroaki Kaneko, Akinori Kanasugi (Tokyo Denki Univ.)
pp. 115 - 120
VLD2016-88
Implementation of Binarized Deep Neural Network for FPGA Considering Power Performance Enhancement
Haruyoshi Yonekawa, Hiroki Nakahara (Tokyo Tech), Masato Motomura (Hokkaido Univ.)
pp. 127 - 132
VLD2016-89
(See Japanese page.)
pp. 133 - 134
VLD2016-90
Kazusa Musha (Keio Univ.), Tomohiro Kudoh (Tokyo Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 135 - 140
VLD2016-91
FPGA Implementation of Mahalanobis Distance-Based Outlier Detection for Streaming Data
Yuto Arai, Shin'ichi Wakabayashi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.)
pp. 141 - 146
VLD2016-92
A New Residue Addition Algorithm Using Signed-Digit Numbers and Its Application to RSA Encryption
Kazumasa Ishikawa, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
pp. 147 - 152
VLD2016-93
Trace-Driven Emulation of Large-Scale Networks-on-Chip on FPGAs
Thiem Van Chu, Kenji Kise (Tokyo Tech)
pp. 153 - 158
VLD2016-94
(See Japanese page.)
pp. 159 - 164
VLD2016-95
Investigation of the influence of input sequences on the calculation accuracy in an approximate operation using a typical circuit
Shimpei Sato, Yuta Ukon, Atsushi Takahashi (Tokyo TECH)
pp. 165 - 170
VLD2016-96
Finite state machine design for high accurate stochastic computing
Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 171 - 174
VLD2016-97
MTJ-based Nonvolatile Flip-Flop Circuit Enabling to Verify Stored Data
Junya Akaike, Kimiyoshi Usami (SIT)
pp. 175 - 180
VLD2016-98
Thermal transient analysis and evaluation of three-dimensional stacked chips
Shogo Yasuda, Kimiyoshi Usami (SIT)
pp. 181 - 186
VLD2016-99
An FPGA NIC Based Distributed Ledger Caching for Blockchain
Yuma Sakakibara, Kohei Nakamura (Keio Univ.), Hiroki Matsutani (Keio Univ./PRESTO/NII)
pp. 203 - 208
VLD2016-100
Proxy Responses for MapReduce Delayed Task Using 10GbE FPGA Switch
Koya Mitsuzuka, Ami Hayashi (Keio Univ.), Hiroki Matsutani (Keio Univ./PRESTO/NII)
pp. 209 - 214
VLD2016-101
Design and Evaluation of A Suboptimal Unidirectional Network
Tomohiro Totoki, Hiroshi Nakahara, Daichi Fujiki (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
pp. 215 - 220
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.