Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
[TOP] | [2013] | [2014] | [2015] | [2016] | [2017] | [2018] | [2019] | [Japanese] / [English]
DC2016-38
A Design Method of Circuits to Generate Stochastic Numbers with the Minimum Inputs
Ritsuko Muguruma, Shigeru Yamashita (Ritsmeikan Univ.)
pp. 1 - 6
DC2016-39
Scheduling of Malleable Fork-Join Tasks
Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 7 - 11
DC2016-40
2-step Charge Pump Voltage Booster Circuit for Micro Energy Harvesting
Tomoya Kimura, Hiroyuki ochi (Ritsumeikan Univ.)
pp. 13 - 18
DC2016-41
Feasibility studies and evaluation for Level-Shifter less design in Silicon-on-Thin-BOX (SOTB)
Shunsuke Kogure, Kimiyoshi Usami (Shibaura Institute of Tech)
pp. 19 - 24
DC2016-42
Implementation Flow of General-Synchronous Circuits from RTL Representation for Xilinx FPGA
Manri Terada, Hayato Mashiko, Yukihide Kohira (Univ. of Aizu)
pp. 25 - 30
DC2016-43
Evaluation of Radiation-Hard Circuit Structures in a FDSOI Process by TCAD Simulations
Kodai Yamada, Haruki Maruoka, Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 31 - 36
DC2016-44
Evaluation of Soft Error Hardness of FinFET and FDSOI Processes by the PHITS-TCAD Simulation System
Shigehiro Umehara, Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 37 - 41
DC2016-45
Evaluation of Soft Error Rates of FlipFlops on FDSOI by Heavy Ions
Masashi Hifumi, Shigehiro Umehara, Haruki Maruoka, Jun Furuta, Kazutoshi Kobayashi (KIT)
pp. 43 - 48
DC2016-46
Circuit Simulation Method Using Bimodal Defect-Centric Model of Random Telegraph Noise on 40 nm SiON Process
Michitarou Yabuuchi, Azusa Oshima, Takuya Komawaki, Kazutoshi Kobayashi, Ryo Kishida, Jun Furuta (KIT), Pieter Weckx (KUL/IMEC), Ben Kaczer (IMEC), Takashi Matsumoto (Univ. of Tokyo), Hidetoshi Onodera (Kyoto Univ.)
pp. 49 - 54
DC2016-47
Design and Implementation Methodology of Low-power Standard cell memory with optimized body-bias separation in Silicon-on-Thin-BOX (SOTB)
Yusuke Yoshida, Kimiyoshi Usami (Shibaura Institute of Tech.)
pp. 55 - 60
DC2016-48
Ultra Low Power Reconfigurable Accelerator CC-SOTB2
Koichiro Masuyama, Naoki Ando, Yusuke Matsushita, Hayate Okuhara, Hideharu Amano (Keio Univ.)
pp. 61 - 66
DC2016-49
FPGA Design and Evaluation of Selector-Logic-based Butterfly Unit
Koki Ito, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 67 - 72
DC2016-50
Accurate Lithography Simulation Model based on Deep Learning
Yuki Watanabe, Tetsuaki Matsunawa, Taiki Kimura, Shigeki Nojima (Toshiba)
pp. 73 - 78
DC2016-51
Length Difference Minimization with Exchanging Pin Pair for Set Pair Routing Problem
Shutaro Hara, Kunihiro Fujiyoshi (TUAT)
pp. 79 - 84
DC2016-52
SADP-Cut Aware Two-color Grid Routing
Hatsuhiko Miura, Mitsuru Hasegawa, Kunihiro Fujiyoshi (TUAT)
pp. 85 - 90
DC2016-53
[Keynote Address]
CMOS Annealing Machine to Solve Combinatorial Optimization Problems for IoT Era
Masanao Yamaoka (Hitachi)
pp. 91 - 96
DC2016-54
[Keynote Address]
The development of video coding technology and contribution to HD transition
Akira Nakagawa (Fujitsu Labs.)
p. 97
DC2016-55
Fast Test Pattern Reordering Based on Weighted Fault Coverage
Shingo Inuyama, Kazuhiko Iwasaki (Tokyo Metropolitan Univ.), Masayuki Arai (Nihon Univ.)
pp. 99 - 104
DC2016-56
Design of TDC Embedded in Scan FFs for Testing Small Delay Faults
Shingo Kawatsuka, Hiroyuki Yotsuyanagi, Masaki Hashizume (Tokushima Univ.)
pp. 105 - 110
DC2016-57
On SAT based test pattern generation for transition faults considering signal activities
Yusuke Matsunaga (Kyushu Univ.)
pp. 111 - 115
DC2016-58
A Method of LRSR Seed Generation for On-chip Fault Diagnosis
Hayato Minamizono, Satoshi Ohtake (Oita Univ.)
pp. 117 - 122
DC2016-59
Partitioned Hash-table and Balanced-tree based FIB Architecture
Kenta Shimazaki (Waseda Univ.), Yuta Ukon, Akihiko Miyazaki (NTT), Toshitaka Tsuda, Hidenori Nakazato, Nozomu Togawa (Waseda Univ.)
pp. 123 - 128
DC2016-60
Malisious tamper detector design with capacitance measurement for IoT devices in operation
Ryosuke Kitayama (Waseda Univ.), Takashi Takenaka (NEC), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 129 - 134
DC2016-61
A Golden-IC Free Clock Tree Driven Authentication Approach for Hardware Trojan Detection
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue (NAIST), Alex Orailoglu (UCSD)
pp. 135 - 140
DC2016-62
An aging aware high-level synthesis algorithm with floorplanning
Koki Igawa, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 141 - 146
DC2016-63
Data Transfer Optimization for Cycle Count and Buffer Size Reduction in Accelerator Design with High-Level Synthesis
Daisuke Ishikawa, Kenshu Seto (TCU)
pp. 147 - 152
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.