Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380
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VLD2014-113
Performance Acceleration of Document-Oriented Stores Using GPUs
Shin Morishima, Hiroki Matsutani (Keio Univ.)
pp. 1 - 6
VLD2014-114
Accelerating NOSQLs using FPGA NIC and In-Kernel Key-Value Cache
Korechika Tamura, Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
pp. 7 - 12
VLD2014-115
An Online Outlier Detector for FPGA NICs
Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
pp. 13 - 18
VLD2014-116
Turbo Boost Router: An On-Chip Router Supporting Deterministic and Adaptive Routings
Natsuki Homma, Go Matsumura (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Hiroki Matsutani (Keio Univ.)
pp. 19 - 24
VLD2014-117
NoC Architecture with Priority-based Packet Overtaking and Resource Control
Shuhei Otsuki, Keigo Mizotani, Masayoshi Takasu (Keio Univ.), Daiki Yamazaki (Sony), Nobuyuki Yamasaki (Keio Univ.)
pp. 25 - 30
VLD2014-118
Radiation tolerance of parallel configuration of optically reconfigurable gate arrays
Hiroyuki Ito, Retsu Moriwaki, Minoru Watanabe (Shizuoka Univ.)
pp. 31 - 34
VLD2014-119
Circuit Design and Valuation of Reconfigurable Logic Circuit.
Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (SIT)
pp. 35 - 40
VLD2014-120
Exploring 3D FPGA Architectures to Minimize the Number of Inter-layer Connections
Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
pp. 41 - 46
VLD2014-121
[Invited Talk]
Human Friendly Robot Based on Ontologies
Takahira Yamaguchi (Keio Univ.)
p. 47
VLD2014-122
An AWF Digital Spectrometer for a Radio Telescope
Hiroki Nakahara (Ehime Univ.), Hiroyuki Nakanishi (Kagoshima Univ.), Kazumasa Iwai (NAOJ)
pp. 67 - 72
VLD2014-123
Small Bandwidth Compression Hardware Exploited Distribution of Length of Prediction Residual
Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 73 - 78
VLD2014-124
Inter-Cube Data-Exchanging for Custom Fluid Computing Machine Based on Building-Cube Method
Tomoya Ueno, Tomohiro Ueno, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)
pp. 79 - 84
VLD2014-125
FPGA Implementation of a High Time Resolution Signal Generation Circuit for PWM
Shun Kashiwagi, Daiki Mitsutake, Hironobu Taniguchi, Yuichiro Shibata, Kiyoshi Oguri, Hidenori Maruta, Fujio Kurokawa (Nagasaki Univ.)
pp. 85 - 90
VLD2014-126
Study on Clock Tree Delay Analysis Mechanism
Goro Suzuki, Ryutaro Takeda (Kitakyushu Univ.)
pp. 91 - 98
VLD2014-127
Temperature sensor applying Body Bias in Silicon-on-Thin-BOX
Tsubasa Kosaka, Shohei Nakamura, Kimiyoshi Usami (S.I.T.)
pp. 99 - 104
VLD2014-128
A Dual-mode Scheduling Strategy for Task Graphs with Data Parallelism
Yang Liu, Lin Meng, Ittetsu Taniguchi, Hiroyuki Tomiyama (Ritsumeikan Univ.)
pp. 105 - 109
VLD2014-129
Analyzing the Impacts of Simultaneous Supply and Threshold Voltage Tuning on Energy Dissipation in VLSI Circuits
Toshihiro Takeshita, Shinichi Nishizawa, AKM Mahfuzul Islam, Tohru Ishihara, Hidetoshi Onodera (Kyoto Univ)
pp. 111 - 116
VLD2014-130
CF3: Test suite for arithmetic optimization of C compilers
Yusuke Hibino, Nagisa Ishiura (KGU)
pp. 117 - 122
VLD2014-131
Discussion on power performance optimization for stream processing on an FPGA accelerator
Kota Fukumoto, Koji Okina, Rie Soejima, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 123 - 128
VLD2014-132
A proposal of a stream image compression architecture using neural networks
Kaoru Hamasaki, Yuichiro Shibata, Kiyoshi Oguri (Nagasaki Univ.)
pp. 129 - 132
VLD2014-133
Intrusion Detection in High-Speed Networks with a Multi-Byte Transition NFA
Shin'ichi Wakabayashi, Tomoaki Hashimoto, Ryohei Koishi, Hiroki Takaguchi, Shinobu Nagayama, Masato Inagi (Hiroshima City Univ.)
pp. 133 - 138
VLD2014-134
Implementation and Evaluation of the Low-level Communication Mechanism on FLOPS-2D
Katsuki Kyan, Makoto Arakaki, Yusuke Hirai, Hiroki Nakasone (Univ. of the Ryukyus), Naoyuki Fujita (JAXA), Hideharu Amano (Keio Univ.), Yasunori Osana (Univ. of the Ryukyus)
pp. 139 - 143
VLD2014-135
A feasibility study on implementing numerical applications on FPGAs using Vivado HLS
Hiroki Nakasone, Yasunori Osana, Yasunori Nagata (Univ of Ryukyu)
pp. 145 - 150
VLD2014-136
Error detection using residue signed-digit number arithmetic for arithmetic circuits
Yoshitomo Nema, Yuuki Tanaka, Kazuhiro Motegi, Shugang Wei (Gunma Univ)
pp. 151 - 156
VLD2014-137
A Hardware Trojan Detection Method based on Trojan net features
Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.)
pp. 157 - 162
VLD2014-138
The proposal of the convex area maze router on LSI design automation
Yohei Horino, Jun Hirayama, Yukiko Ohishi, Toshiyuki Tsutsumi (Meiji Univ.)
pp. 163 - 168
VLD2014-139
Detecting Missed Arithmetic Optimization Opportunities Using Random Testing of C Compilers
Atsushi Hashimoto, Nagisa Ishiura (Kwansei Gakuin Univ.)
pp. 169 - 174
VLD2014-140
An FPGA Implementation of Deep Convolutional Neural Network using Synchronous Shift Data Transfer
Li Ning, Yoichi Tomioka, Hitoshi Kitazawa (TUAT)
pp. 175 - 180
VLD2014-141
Implementation of Sparse Matrix-Vector Multiplication on GPU and Its Application to the Conjugate Gradient Method
Shotaro Asano, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.)
pp. 181 - 186
VLD2014-142
Relaxing constraint conditions in parallelizing compiler based on a polyhedral model
Toma Ogata, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.)
pp. 187 - 192
VLD2014-143
Acceleration of Big Data Partitioning with Multiple FPGA boards
Ryu Kudo, Saori Sudo, Yasin Oge (UEC), Yuta Terada (AVAL DATA), Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga (UEC)
pp. 193 - 198
VLD2014-144
Reliability Management in 2-layered Supervisor Processor
Daiki Yamamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ)
pp. 199 - 204
VLD2014-145
Design and Implementation of Portable and High-speed FPGA Accelerator employing USB3.0
Takuma Usui, Ryohei Kobayashi, Kenji Kise (Tokyo Tech)
pp. 205 - 210
VLD2014-146
MieruSys Project : Developing an Advanced Computer System with Multiple FPGAs
Yuki Matsuda, Eri Ogawa, Tomohiro Misono (Tokyo Tech), Naoki Fujieda, Shuichi Ichikawa (TUT), Kenji Kise (Tokyo Tech)
pp. 211 - 216
VLD2014-147
FPGA Vendor Independent Descriptions and Designs of Synchronous FIFOs
Tomonori Izumi (Ritsumeikan Univ.)
pp. 217 - 220
VLD2014-148
Obfuscated Hardware Implementation of PLC Instructions with Opaque Predicates
Kazuki Uyama, Naoki Fujieda, Shuichi Ichikawa (Toyohashi Tech.)
pp. 221 - 226
VLD2014-149
A Low Latency Real-Time Execution on Dependable Responsive Multithreaded Processor
Keigo Mizotani, Yusuke Hatori, Yusuke Kumura, Masayoshi Takasu, Hiroyuki Chishiro, Nobuyuki Yamasaki (Keio Univ.)
pp. 227 - 232
VLD2014-150
A Latency-Aware Packet Scheduling on Responsive Link
Kouhei Oosawa, Shuma Hagiwara, Yusuke Kumura, Keigo Mizotani, Masayoshi Takasu, Nobuyuki Yamasaki (Keio Univ.)
pp. 233 - 238
VLD2014-151
Real-time contour extraction for moving objects directly operating MPEG encoded data
Syosuke Maruyama, Hidehiro Nakano, Arata Miyauchi (Tokyo City Univ.)
pp. 239 - 244
VLD2014-152
A Cache to Cache Communication Strategy for Wireless 3D Multi-Core Processors
Masataka Matsumura (UEC), Masaaki Kondo (Univ. Tokyo), Hiroki Matsutani (Keio Univ.), Yasutaka Wada (Waseda Univ.), Hiroki Honda (UEC)
pp. 245 - 250
Note: Each article is a technical report without peer review, and its polished version will be published elsewhere.