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“dŽqî•ñ’ÊMŠw‰ï˜_•¶ŽiD), ‚U‚O|D,@‚QC‚‚D‚P‚T‚P|‚P‚T‚WCFeb.@‚P‚X‚V‚VD
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K. Ueda, H.Kitazawa,
"CHAMP: Chip Floor Plan for Hierarchical VLSI Design,"
IEEE Trans on CAD, Vol.4, No.1, pp.12-22, Jan. 1985.
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K. Ueda, H. Kitazawa,
"Top-down Layout for Hierarchical CustomDesign,"
IEEE Design & Test, Vol. 4, No. 6, pp.22-29, Jan. 1987.
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