In our information society demanding ever-increasing performance of integrated circuits, FinFETs, which have advanced transistor structures succeeding the traditional planar transistor, are widely used today for commercial products. In designing the physical layout of digital logic gates using FinFET technology, a fundamental issue arises: if FinFETs are placed too close to one another, they can become electrically connected through leakage currents, thereby degrading circuit reliability. A common solution to this problem is to increase the spacing between FinFETs. In particular, a structure where two dummy polysilicon gates are interposed between FinFETs is known as a Double Diffusion Break (DDB) structure. While DDB is an effective technique for enhancing reliability, it poses a significant challenge by reducing the integration density of the FinFETs.

To simultaneously improve the area efficiency and reliability of digital logic circuits, the authors propose a method that physically shares equipotential nodes between FinFETs in each logic gate, achieving both high reliability and area reduction. Despite utilizing a high-density Single Diffusion Break (SDB) structure, where FinFETs are separated by only a single dummy polysilicon gate, reliability degradation due to leakage current is significantly mitigated because the adjacent FinFETs maintain the same potential. The authors have developed a layout generation algorithm that automatically solves this placement optimization problem during the design of digital logic gates. Experimental results using a virtual 7nm process technology show that digital circuits synthesized with the proposed logic gate library achieve an average area reduction of 8.39% compared with those using a baseline library, while still satisfying DDB/SDB-derived placement constraints. These results indicate that higher density can be achieved solely through innovations in design technology without further process scaling, representing substantial practical value.

The results of this research contribute significantly to the optimization of Power, Performance, and Area (PPA) in advanced processes and are expected to serve as an essential guideline for circuit design in future scaled generation.