With the miniaturization of MOSFETs (MOSTs), the supply voltage and threshold voltage should be reduced so that a 6-transistor memory cell (6T cell) SRAM has problems such as decreased read/write margins, read and write operation failures at low voltage and increased current leakage. Dual power supply SRAM and 8T cell SRAM have been proposed to solve the above problems. However, new problems have arisen, such as adding a power supply and increasing chip area.

In order to realize a high-performance SRAM with a single power supply and 6T cells, we have developed a Self-controlled Voltage Level translation (SVL) circuit which has an extremely simple structure consisting of only three MOSTs.

During writing and standby a pMOST and an nMOST, in the SVL circuit (M-SVL) dedicated to the memory cell array (MA) are turned off and turned on, respectively, so that the external voltage (VDD) is rapidly stepped down by the amount of the nMOST threshold voltage (vt). Then, the stepped down voltage (VDD - vt) is supplied to the MA. At the same time, the pMOST discharge switch is only turned on for a short time. On the other hand, during reading, nMOST is turned off, pMOST is turned on, and VDD is supplied to the MA.

During reading a pMOST and an nMOST, in the SVL circuit (W-SVL) dedicated to the word-line driver (WD) are turned off and turned on, respectively, so that the stepped down voltage (VDD - vt) is supplied to the WD. During writing, the pMOST and nMOST are turned on and turned off, respectively, so that VDD is supplied to the WD. During standby both pMOST and nMOST are turned off and the an nMOST discharge switch is turned on for a short time, so VDD is stepped down to 0V and supplied to the WD.

We fabricated a single power supply, 6T cell SRAM equipped with eight M-SVLs and a single W-SVL using 90nm CMOS technology. The write and read margins of the newly developed SRAM have been expanded (improved) to 1.309 times and 2.093 times, respectively, compared to a conventional SRAM that does not include an SVL circuit. The minimum write voltage for the conventional SRAM was 0.37V, but it has been reduced (improved) to 0.22V for the newly developed SRAM. The minimum read voltage for conventional SRAM was 1.05V, but for the developed SRAM it has been reduced (improved) to 0.41V. At VDD =1V and data retention state, power consumption due to the leakage current of the conventional SRAM and developed SRAM was 10.12 µW and 0.957 µW, respectively. Compared to the former, the latter was significantly reduced (improved) to 9.46%. The area overhead of the SVL circuit is extremely small, at only 1.383% of the total area of the developed SRAM.

The newly developed SVL circuit for 6T cell SRAM is an extremely effective circuit technology that improves the read/write margin, lowers the minimum read/write voltage, and simultaneously retains data and reduces power consumption during standby.