| IEICE Technical Committee Submission System Conference Schedule |
Online Proceedings [Sign in] Tech. Rep. Archives |
Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2014)
Search Results: Keywords 'from:2014-11-26 to:2014-11-26'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita | B-ConPlaza | A complex multiplier using two floating-point fused multiply-add unit Yuhei Takata, Naofumi Takagi, Kazuyoshi Takagi (Kyoto Univ.)  CPSY2014-76 |
Complex operations are used in scientific computing and signal processing. Floating-point complex multiplication is imp... [more] |
CPSY2014-76 pp.25-29 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 10:45 |
Oita | B-ConPlaza | A hardware description method and sematics providing a timing constrant Shunji Nishimura, Motoki Amagasaki, Toshinori Sueyoshi (Kumamoto Univ.) VLD2014-82 DC2014-36 |
Formal verification methods are wide-spreading due to its mathmatical rigorousaspect, although they limited to synchroun... [more] | VLD2014-82 DC2014-36 pp.81-86 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 11:10 |
Oita | B-ConPlaza | Technology Mapping Method for Low Power Consumption and High Performance in General-Synchronous Framework Junki Kawaguchi, Yukihide Kohira (Univ. of Aizu) VLD2014-83 DC2014-37 |
In general-synchronous framework, in which the clock is distributed periodically to each register but not necessarily si... [more] | VLD2014-83 DC2014-37 pp.87-92 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 11:35 |
Oita | B-ConPlaza | Voltage Dependence of Single Event Transient Pulses on 65nm Silicon-on-Thin-BOX and Bulk Processes Eiji Sonezaki, Kuiyuan Zhang, Jun Furuta, Kazutoshi Kobayashi (Kyoto Inst. of Tech.) VLD2014-84 DC2014-38 |
Recently, the growth of power consumption has been serious by process scaling. The lower voltage is most effective to i... [more] |
VLD2014-84 DC2014-38 pp.93-97 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 14:45 |
Oita | B-ConPlaza | A Floorplan-aware High-level Synthesis Algorithm Utilizing Interconnection Delay Characteristics in FPGA Designs Koichi Fujiwara, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-85 DC2014-39 |
Recently, high-level synthesis (HLS) techniques for FPGA designs are required such as in image pro- cessing and computer... [more] | VLD2014-85 DC2014-39 pp.99-104 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:10 |
Oita | B-ConPlaza | A Process-Variation-Tolerant and Low-Latency Multi-Scenario High-level Synthesis Algorithm for HDR Architectures Koki Igawa, Shin-ya Abe, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-86 DC2014-40 |
In this paper, we propose a process-variation-tolerant and low-latency multi-scenario high-level synthesis algorithm for... [more] | VLD2014-86 DC2014-40 pp.105-110 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 15:35 |
Oita | B-ConPlaza | A Method for Total Length and Length Difference Reduction for Set-Pair Routing Yuta Nakatani, Atsushi Takahashi (Titech) VLD2014-87 DC2014-41 |
Set pair routing problem in which connection requirements are given between a pair of terminals is a routing problem on... [more] |
VLD2014-87 DC2014-41 pp.111-116 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:15 |
Oita | B-ConPlaza | High speed design of sub-threshold circuit by using DTMOS Yuji Fukudome, Youhua Shi, Nozomu Togawa (Waseda Univ.), Kimiyoshi Usami (Shibaura Inst. of Tech), Masao Yanagisawa (Waseda Univ.) VLD2014-88 DC2014-42 |
Low power consumption is achieved by operating circuits in sub-threshold region. However, in sub-threshold region, the... [more] |
VLD2014-88 DC2014-42 pp.117-121 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 16:40 |
Oita | B-ConPlaza | Don't-Care Extension in Logic Synthesis for Error Tolerant Application Tomoya Inaoka, Hideyuki Ichihara, Tsuyoshi Iwagaki, Tomoo Inoue (Hiroshima City Univ.) VLD2014-89 DC2014-43 |
In logic synthesis for error tolerant applications, external observability don’t-cares can be freely enhanced within a g... [more] | VLD2014-89 DC2014-43 pp.123-128 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:05 |
Oita | B-ConPlaza | Selection of Check Variables for Area-Efficient Soft-Error Tolerant Datapath Synthesis Junghoon Oh, Mineo Kaneko (JAIST) VLD2014-90 DC2014-44 |
As the device size decreases, the reliability degradation caused by soft-errors becomes one of the greatest issues in cu... [more] | VLD2014-90 DC2014-44 pp.129-134 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-26 17:30 |
Oita | B-ConPlaza | A Hardware Trojans Detection Method focusing on Nets in Hardware Trojans in Gate-Level Netlists Masaru Oya, Youhua Shi, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-91 DC2014-45 |
Recently, digital ICs are designed by outside vendors to reduce design costs in semiconductor industry. This circumstan... [more] |
VLD2014-91 DC2014-45 pp.135-140 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 13:30 |
Oita | B-ConPlaza | [Invited Talk]
Magnetic Resonance (MR) Safety of Implantable Medical Device: Current Status and Future Prospect Kagayaki Kuroda (Tokai Univ.) VLD2014-92 CPM2014-122 ICD2014-65 CPSY2014-77 DC2014-46 RECONF2014-40 |
[more] | VLD2014-92 CPM2014-122 ICD2014-65 CPSY2014-77 DC2014-46 RECONF2014-40 pp.141-144(VLD), pp.1-4(CPM), pp.1-4(ICD), pp.31-34(CPSY), pp.141-144(DC), pp.37-40(RECONF) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 14:45 |
Oita | B-ConPlaza | [Invited Talk]
Latest Development and Future Prospect of Mobile Display Technology Yoshiharu Nakajima (JDI) VLD2014-93 CPM2014-123 ICD2014-66 CPSY2014-78 DC2014-47 RECONF2014-41 |
Together with wide spread of mobile phone and smart phone, mobile display technology is developing for high resolution, ... [more] | VLD2014-93 CPM2014-123 ICD2014-66 CPSY2014-78 DC2014-47 RECONF2014-41 pp.145-148(VLD), pp.5-8(CPM), pp.5-8(ICD), pp.35-38(CPSY), pp.145-148(DC), pp.41-44(RECONF) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:00 |
Oita | B-ConPlaza | Timing-Test Scheduling for PDE Tuning Considering Multiple-Path Testability Mineo Kaneko (JAIST) VLD2014-94 DC2014-48 |
[more] | VLD2014-94 DC2014-48 pp.149-154 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:50 |
Oita | B-ConPlaza | On implicit enumeration of vector pairs for synthesizing index generator Yusuke Matsunaga (Kyushu Univ.) VLD2014-95 DC2014-49 |
[more] | VLD2014-95 DC2014-49 pp.161-165 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:00 |
Oita | B-ConPlaza | Integrated-Circuit Countermeasures Against Side-Channel Information Leakage Noriyuki Miura, Daisuke Fujimoto, Makoto Nagata (Kobe University) CPM2014-124 ICD2014-67 |
This paper describes integrated-circuit countermeasures against information leakage from cryptographic processor ICs thr... [more] | CPM2014-124 ICD2014-67 pp.9-14 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:25 |
Oita | B-ConPlaza | Design and study of PUF Circuit using IO-Masked Dual-Rail ROM with Resistance against Side-Channel Attacks Takashi Nishimura, Akihiro Takeuchi, Mitsuru Shiozaki, Takeshi Fujino (Ritsumeikan Univ.) CPM2014-125 ICD2014-68 |
Physical unclonable function (PUF) has been proposed as tamper-resistant technique to protect secure device. The PUF ext... [more] | CPM2014-125 ICD2014-68 pp.15-20 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:50 |
Oita | B-ConPlaza | Circuit Design of Reconfigurable Dynamic Logic Junki Kato, Shigeyoshi Watanabe, Hiroshi Ninomiya, Manabu Kobayashi, Yasuyuki Miura (Shonan Inst. of Tech.) CPM2014-126 ICD2014-69 |
[more] | CPM2014-126 ICD2014-69 pp.21-26 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:00 |
Oita | B-ConPlaza | Design and Evaluation of High-speed Serial Communication Mechanism for FPGA-based ASIC Emulator Takashi Okamoto, Morihiro Kuga, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2014-42 |
The circuit scale of Application Specific Integrated Circuit（ASIC）has been increasing. Therefore the shortening of funct... [more] | RECONF2014-42 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:25 |
Oita | B-ConPlaza | Voice Recognition System using hw/sw Complex Yuichi Ogishima, Jiang Li, Satoru Yokota, Hiromasa Kubo, Masatoshi Sekine (TUAT) RECONF2014-43 |
To assign processor having big load to the FPGA which is LSI being reconfigurable to Hardware and SoftWare complex , the... [more] | RECONF2014-43 pp.51-56 |
[Return to Top Page]