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Technical Committee on Reconfigurable Systems (RECONF) (Searched in: 2014)
Search Results: Keywords 'from:2014-11-26 to:2014-11-26'
| Committee | Date Time | Place | Paper Title / Authors | Abstract | Paper # | |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-27 16:50 |
Oita | B-ConPlaza | Accelerating finite field arithmetic with a suitable word size Aiko Iwasaki, Yuichiro Shibata, Kiyoshi Oguri, Ryuichi Harasawa (Nagasaki Univ.)  RECONF2014-44 |
In this paper, we implement architecture to speed up $GF(2^m)$ arithmetic in Elliptic Curve Cryptography(ECC) systems as... [more] | RECONF2014-44 pp.57-61 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Scalable and Low Latency Structure for Castle of Chips Hiroshi Nakahara, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) CPSY2014-79 |
Castle of Chips(CoC) is a chip stacking structure without chip-to-chip wired interconnection. Instead, each chip uses in... [more] | CPSY2014-79 pp.39-44 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | A Distributed Router Architecture using transparent latches for Networks-on-Chip Ryota Yasudo, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano, Tadao Nakamura (Keio Univ.) CPSY2014-80 |
Technology scaling creates NoC bottlenecks in both energy and delay, so especially wire delays and the power consumptio... [more] |
CPSY2014-80 pp.45-50 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | Implementation and Evaluation of An Accelerator based on Manymemory Network Ryo Shimizu, Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-81 |
In this research, we focus on the data parallelization of stencil computations on a previously proposed memory-network b... [more] | CPSY2014-81 pp.51-56 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:30 |
Oita | B-ConPlaza | Convolutional Neural Network Processing on An Accelerator based on Manymemory Network Masakazu Tanomoto, Shinya Takamaeda-Yamazaki, Jun Yao, Yasuhiko Nakashima (NAIST) CPSY2014-82 |
Recently, Convolutional Neural Network (CNN) is widely used for image recognition. GPU is generally preferred to acceler... [more] | CPSY2014-82 pp.57-62 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 11:10 |
Oita | B-ConPlaza | [Fellow Memorial Lecture]
Looking Back over My Researches on Flexible Hardware
-- Reconfigurable Systems and FPGAs -- Toshinori Sueyoshi (Kumamoto Univ.) CPSY2014-83 |
As IEICE Fellow commemorative lecture, I look back over my researches of more than 30 years on Flexible Hardware such as... [more] | CPSY2014-83 pp.63-68 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 13:30 |
Oita | B-ConPlaza | [Invited Talk]
A 56-Gb/s Receiver Front-End with a CTLE and 1-Tap DFE in 20-nm CMOS Yasufumi Sakai, Takayuki Shibasaki, Takumi Danjo, Hisakatsu Yamaguchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura (Fujitsu LAB.) VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45 |
To meet ever-increasing demands for computing power in data centers, data rates over 50Gbps/signal (e.g., OIF CEI-56G-VS... [more] | VLD2014-96 CPM2014-127 ICD2014-70 CPSY2014-84 DC2014-50 RECONF2014-45 pp.167-172(VLD), pp.27-32(CPM), pp.27-32(ICD), pp.69-74(CPSY), pp.167-172(DC), pp.63-68(RECONF) |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 14:45 |
Oita | B-ConPlaza | [Invited Talk]
25-Gb/s CMOS Optical Transceiver for Board-to-board Interconnects Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka (Hitachi) CPM2014-128 ICD2014-71 |
The current explosive increase in the data traffic causes a rapid expansion in the total throughput for board-to-board s... [more] | CPM2014-128 ICD2014-71 pp.33-38 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | [Invited Talk]
An approach for 30Gb/s optical LSI volume testing Daisuke Watanabe (Advantest), Shin Masuda (ADVANTEST Lab) CPM2014-129 ICD2014-72 |
With increasing data transmission capacity due to cloud computing, datacenters have an increased need for lower power an... [more] | CPM2014-129 ICD2014-72 pp.39-42 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Note on Weighted Fault Coverage Considering Multiple Defect Sizes and Via Open Masayuki Arai (Nihon Univ.), Yuta Nakayama, Kazuhiko Iwasaki (Tokyo Metro. Univ.) VLD2014-97 DC2014-51 |
[more] | VLD2014-97 DC2014-51 pp.173-178 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | A Test Generation Method for Low Capture Power Using Capture Safe Test Vectors Atsushi Hirai, Toshinori Hosokawa, Yukari Yamauchi, Masayuki Arai (Nihon Univ.) VLD2014-98 DC2014-52 |
In at-speed scan testing, capture power is a serious problem because the high power dissipation that can occur when the ... [more] | VLD2014-98 DC2014-52 pp.179-184 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | A Test Point Insertion Method to Reduce Capture Power Dissipation Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2014-99 DC2014-53 |
In at-speed scan testing of deep sub-micron era, high power dissipation can occur by high launch-induced switching activ... [more] | VLD2014-99 DC2014-53 pp.185-190 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:30 |
Oita | B-ConPlaza | A Multi Cycle Capture Test Generation Method to Reduce Capture Power Dissipation Hiroshi Yamazaki, Jun Nishimaki, Toshinori Hosokawa (Nihon Univ.), Masayoshi Yoshimura (Kyoto Sangyo Univ.) VLD2014-100 DC2014-54 |
[more] | VLD2014-100 DC2014-54 pp.191-196 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 14:45 |
Oita | B-ConPlaza | A Study of Power Optimization for Asynchronous Circuits with Bundled-data Implementation using Mobility of Operations Shunya Hosaka, Hiroshi Saito (Univ. Aizu) VLD2014-104 DC2014-58 |
In this paper, we study a dynamic power optimization method for asynchronous circuits with bundled-data implementation u... [more] | VLD2014-104 DC2014-58 pp.215-220 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:10 |
Oita | B-ConPlaza | A Field Data Extractor Configuration Based on Multiplexer Tree Partitioning Koki Ito, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.), Yutaka Tamiya (Fujitsu Lab.) VLD2014-101 DC2014-55 |
As seen in packet analysis of TCP/IP offload engine and stream data processing of encoder/decoder for video data, it is ... [more] | VLD2014-101 DC2014-55 pp.197-202 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 15:35 |
Oita | B-ConPlaza | Energy-efficient High-level Synthesis Algorithm targeting HDR-mcv Architecture with Multiple Clock Domains and Multiple Supply Voltages Shin-ya Abe, Youhua Shi (Waseda Univ.), Kimiyoshi Usami (Shibaura Institute of Technology/Waseda Univ.), Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-102 DC2014-56 |
An HDR-mcv architecture, which integrates multiple supply voltages and multiple clock domains into high-level synthesis ... [more] | VLD2014-102 DC2014-56 pp.203-208 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 16:00 |
Oita | B-ConPlaza | A High-level Synthesis Algorithm with Delay Variation Tolerance Optimization for RDR Architectures Yuta Hagio, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-103 DC2014-57 |
In this paper, we propose a high-level synthesis algorithm with delay variation tolerance optimization for RDR architect... [more] | VLD2014-103 DC2014-57 pp.209-214 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:15 |
Oita | B-ConPlaza | Energy evaluation of bit-write reduction method based on state encoding limiting maximum and minimum Hamming distances for non-volatile memories Tatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-105 DC2014-59 |
Data stored in non-volatile memories may be destructed due to crosstalk and radiation but we can restore their data by u... [more] | VLD2014-105 DC2014-59 pp.221-226 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 09:40 |
Oita | B-ConPlaza | Small-Sized Encoder/Decoder Circuit Design for Bit-Write Reduction Targeting Non-Volatile Memories Masashi Tawada, Shinji Kimura, Masao Yanagisawa, Nozomu Togawa (Waseda Univ.) VLD2014-106 DC2014-60 |
Non-volatile memory has many advantages such as low leakage power and non-volatility. However, there are problems that ... [more] |
VLD2014-106 DC2014-60 pp.227-232 |
| VLD, DC, IPSJ-SLDM, CPSY, RECONF, ICD, CPM (Joint) [detail] |
2014-11-28 10:05 |
Oita | B-ConPlaza | Optimization for gate-level pipelined self-synchrnous circuit Atsushi Ito, Makoto Ikeda (Univ. of Tokyo) VLD2014-107 DC2014-61 |
With the down-scaling, circuit which has higher robustness is demanded. Dual-pipeline self synchronous circuit have inhe... [more] | VLD2014-107 DC2014-61 pp.233-238 |
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