| IEICE Technical Committee Submission System Advance Program |
Online Proceedings [Sign in] Tech. Rep. Archives |
| Go Top | Go Back | Prev CPSY Conf / Next CPSY Conf | [HTML] / [HTML(simple)] / [TEXT] | [Japanese] / [English] |
|
=============================================== Technical Committee on Computer Systems (CPSY) Chair: Koji Nakano (Hiroshima Univ.) Vice Chair: Hidetsugu Irie (Univ. of Tokyo), Takashi Miyoshi (Fujitsu) Secretary: Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (Hokkaido Univ.) Assistant: Yasuaki Ito (Hiroshima Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.) =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Hiroyuki Ochi (Ritsumeikan Univ.) Vice Chair: Noriyuki Minegishi (Mitsubishi Electric) Secretary: Shinobu Nagayama (Hiroshima City Univ.), Koyo Nitta (NTT) =============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Masato Motomura (Hokkaido Univ.) Vice Chair: Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (Tohoku Univ.) Secretary: Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan) Assistant: Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.) =============================================== Special Interest Group on System Architecture (IPSJ-ARC) Chair: Masahiro Goshima (NII) Secretary: Takatsugu Ono (Kyushu Univ.), Masaaki Kondo (Univ. of Tokyo), Yohei Hasegawa (Toshiba), Ryota Shioya (Nagoya Univ.) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Kiyoharu Hamaguchi (Shimane Univ.) Secretary: Ko Kyo (Panasonic), Yukio Mitsuyama (Kochi Univ. of Tech.), Seiya Shibata (NEC) DATE: Thu, Jan 18, 2018 09:15 - 20:00 Fri, Jan 19, 2018 09:15 - 17:05 PLACE: TOPICS: FPGA Applications, etc ---------------------------------------- Thu, Jan 18 AM (09:15 - 10:30) Chair: Makoto Motomura (Hokkaido Univ) ---------------------------------------- (1)/CPSY 09:15 - 09:40 Yugo Yamauchi, Kazusa Musha (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.) (2)/RECONF 09:40 - 10:05 All Binarized Conventional Neural Network and its Implementation on an FPGA -- FPT2017 Design Competition Report -- Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech) (3)/RECONF 10:05 - 10:30 An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 18 AM (10:40 - 11:55) ---------------------------------------- (4)/CPSY 10:40 - 11:05 Kazutaka Ogihara (Fujitsu Lab.) (5)/CPSY 11:05 - 11:30 Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.) (6)/CPSY 11:30 - 11:55 (See Japanese page.) ----- Lunch Break ( 65 min. ) ----- ---------------------------------------- Thu, Jan 18 PM (13:00 - 14:15) ---------------------------------------- (7)/VLD 13:00 - 13:25 Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs Kaori Tajima, Masahiro Inoue, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.) (8)/VLD 13:25 - 13:50 Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.) (9)/VLD 13:50 - 14:15 Examination of the Normally-off using the stack circuit Kenji Sakamura (OPUGS), Kazutami Arimoto, Isao Kayano, Tomoyuki Yokogawa (OPU) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 18 PM (14:25 - 15:25) ---------------------------------------- (10)/CPSY 14:25 - 15:25 (See Japanese page.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 18 PM (15:35 - 16:25) Chair: Kazuya Tanigawa (Hiroshima City Univ.) ---------------------------------------- (11)/RECONF 15:35 - 16:00 (See Japanese page.) (12)/RECONF 16:00 - 16:25 Integrated Machine Code Monitor on FPGA Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, Jan 18 PM (16:35 - 17:25) Chair: Hiroki Nakahara (Tokyo Tech) ---------------------------------------- (13)/RECONF 16:35 - 17:00 Daichi Tanaka, Antoniette Mondigo, Kentaro Sano, Satoru Yamamoto (Tohoku Univ) (14)/VLD 17:00 - 17:25 Distributed Memory Architecture for High-Level Synthesis from Erlang Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM) ----- Break ( 35 min. ) ----- ---------------------------------------- Thu, Jan 18 PM (18:00 - 20:00) ---------------------------------------- ---------------------------------------- Fri, Jan 19 AM (09:15 - 10:30) Chair: Kentaro Sano (Tohoku Univ.) ---------------------------------------- (15)/RECONF 09:15 - 09:40 FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT) (16)/RECONF 09:40 - 10:05 Overview of an HLS Framework Surpporting IoT/CPS Development Daichi Teruya, Hironori Nakajo (TUAT) (17)/RECONF 10:05 - 10:30 Automatic Conversion from Snort PCRE to Verilog HDL Masahiro Fukuda, Yasushi Inoguchi (JAIST) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Jan 19 AM (10:40 - 11:55) ---------------------------------------- (18)/VLD 10:40 - 11:05 Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.) (19)/VLD 11:05 - 11:30 A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.) (20)/RECONF 11:30 - 11:55 Total-ionizing-dose tolerance of an optically reconfigurable gate array Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.) ----- Lunch Break ( 65 min. ) ----- ---------------------------------------- Fri, Jan 19 PM (13:00 - 14:15) ---------------------------------------- (21)/RECONF 13:00 - 13:25 FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (22) 13:25 - 13:50 (23)/CPSY 13:50 - 14:15 Accelerating Sequential Learning Algorithm OS-ELM Using FPGA-NIC Mineto Tsukada, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Jan 19 PM (14:25 - 15:40) ---------------------------------------- (24)/CPSY 14:25 - 14:50 Accelerating Serialization Protocols for Network-Attached FPGAs Takuma Iwata, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.) (25)/RECONF 14:50 - 15:15 (See Japanese page.) (26)/RECONF 15:15 - 15:40 Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs Yoshio Murata, Hironori Nakajo (TUAT) ----- Break ( 10 min. ) ----- ---------------------------------------- Fri, Jan 19 PM (15:50 - 17:05) ---------------------------------------- (27) 15:50 - 16:15 (28)/VLD 16:15 - 16:40 Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation Mitsuyoshi Iwatsuji, Nagisa Ishiura (Kwansei Gakuin Univ.) (29)/VLD 16:40 - 17:05 Mutant Generation of Performance Tests for LLVM Back-Ends Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas) # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Wed, Mar 7, 2018 - Thu, Mar 8, 2018: Okinoshima Bunka-Kaikan Bldg. [Fri, Jan 12], Topics: ETNET2018 # SECRETARY: Takashi Miyoshi (FUJITSU) TEL +81-44-754-2931, FAX +81-44-754-2672 E-mail:            CPSY WEB http://www.ieice.or.jp/iss/cpsy/jpn/ === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Wed, Feb 28, 2018 - Fri, Mar 2, 2018: Okinawa Seinen Kaikan [Mon, Jan 15] # SECRETARY: Shinobu Nagayama (Hiroshima City University) E-mail: s_      -cu # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Masato Motomura（Hokkaido Univ.） E-mail:     ist   iYuki Kobayashi (NEC) E-mail: y-  ba hq c# ANNOUNCEMENT: # http://www.ieice.org/~reconf/ === Special Interest Group on System Architecture (IPSJ-ARC) === # FUTURE SCHEDULE: Wed, Mar 7, 2018 - Thu, Mar 8, 2018: Okinoshima Bunka-Kaikan Bldg. [Fri, Jan 12], Topics: ETNET2018 === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Wed, Mar 7, 2018 - Thu, Mar 8, 2018: Okinoshima Bunka-Kaikan Bldg. [Fri, Jan 12], Topics: ETNET2018 # SECRETARY: Yukio Mitsuyama (Kochi Univ. of Tech.) E-mail:   o - # ANNOUNCEMENT: # Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/ Last modified: 2018-01-10 11:01:25 |
Notification: Mail addresses are partially hidden against SPAM.
[Download Paper's Information (in Japanese)] <-- Press download button after click here.
[Cover and Index of IEICE Technical Report by Issue]
[Presentation and Participation FAQ] (in Japanese)
[Return to VLD Schedule Page] / [Return to CPSY Schedule Page] / [Return to RECONF Schedule Page] / [Return to IPSJ-ARC Schedule Page] / [Return to IPSJ-SLDM Schedule Page] /
| Go Top | Go Back | Prev CPSY Conf / Next CPSY Conf | [HTML] / [HTML(simple)] / [TEXT] | [Japanese] / [English] |
[Return to Top Page]