ken-system: Advance Program - 2018-01-IPSJ-ARC-VLD-CPSY-RECONF-IPSJ-SLDM

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Technical Committee on Computer Systems (CPSY)

[schedule] [select]

Chair		Koji Nakano (Hiroshima Univ.)
Vice Chair		Hidetsugu Irie (Univ. of Tokyo), Takashi Miyoshi (Fujitsu)
Secretary		Takeshi Ohkawa (Utsunomiya Univ.), Shinya Takameda (Hokkaido Univ.)
Assistant		Yasuaki Ito (Hiroshima Univ.), Tomoaki Tsumura (Nagoya Inst. of Tech.)

Technical Committee on VLSI Design Technologies (VLD)

[schedule] [select]

Chair		Hiroyuki Ochi (Ritsumeikan Univ.)
Vice Chair		Noriyuki Minegishi (Mitsubishi Electric)
Secretary		Shinobu Nagayama (Hiroshima City Univ.), Koyo Nitta (NTT)

Technical Committee on Reconfigurable Systems (RECONF)

[schedule] [select]

Chair		Masato Motomura (Hokkaido Univ.)
Vice Chair		Yuichiro Shibata (Nagasaki Univ.), Kentaro Sano (Tohoku Univ.)
Secretary		Kazuya Tanigawa (Hiroshima City Univ.), Takefumi Miyoshi (e-trees.Japan)
Assistant		Yuuki Kobayashi (NEC), Hiroki Nakahara (Tokyo Inst. of Tech.)

Special Interest Group on System Architecture (IPSJ-ARC)

[schedule] [select]

Chair		Masahiro Goshima (NII)
Secretary		Takatsugu Ono (Kyushu Univ.), Masaaki Kondo (Univ. of Tokyo), Yohei Hasegawa (Toshiba), Ryota Shioya (Nagoya Univ.)

Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM)

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Chair		Kiyoharu Hamaguchi (Shimane Univ.)
Secretary		Ko Kyo (Panasonic), Yukio Mitsuyama (Kochi Univ. of Tech.), Seiya Shibata (NEC)

Conference Date	Thu, Jan 18, 2018 09:15 - 20:00 Fri, Jan 19, 2018 09:15 - 17:05
Topics	FPGA Applications, etc
Conference Place
Registration Fee	This workshop will be held as the IEICE workshop in fully electronic publishing. Registration fee will be necessary except the speakers and participants other than the participants to workshop(s) in non-electronic publishing. See the registration fee page. We request the registration fee or presentation fee to participants who will attend the workshop(s) on CPSY, RECONF.

Thu, Jan 18 AM Chair: Makoto Motomura (Hokkaido Univ) 09:15 - 10:30
(1) CPSY	09:15-09:40		Yugo Yamauchi, Kazusa Musha (Keio Univ.), Kudoh Tomohiro (Univ. of Tokyo), Hideharu Amano (Keio Univ.)
(2) RECONF	09:40-10:05	All Binarized Conventional Neural Network and its Implementation on an FPGA -- FPT2017 Design Competition Report --	Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara (titech)
(3) RECONF	10:05-10:30	An Implementation of a Binarized Deep learning Neural Network on an FPGA using the Intel OpenCL	Takumu Uyama, Tomoya Fujii, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara (Titech)
	10:30-10:40	Break ( 10 min. )
Thu, Jan 18 AM 10:40 - 11:55
(4) CPSY	10:40-11:05		Kazutaka Ogihara (Fujitsu Lab.)
(5) CPSY	11:05-11:30		Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)
(6) CPSY	11:30-11:55
	11:55-13:00	Lunch Break ( 65 min. )
Thu, Jan 18 PM 13:00 - 14:15
(7) VLD	13:00-13:25	Reducing Power Consumption for Circuits Dedicated to Image Sharpening Processing using CMAs	Kaori Tajima, Masahiro Inoue, Hiroyuki Baba, Tongxin Yang, Tomoaki Ukezono, Toshinori Sato (Fukuoka Univ.)
(8) VLD	13:25-13:50	Residue-weighted number conversion based on Signed-Digit arithmetic for a four moduli set	Kouhei Yamazaki, Yuuki Tanaka, Shugang Wei (Gunma Univ.)
(9) VLD	13:50-14:15	Examination of the Normally-off using the stack circuit	Kenji Sakamura (OPUGS), Kazutami Arimoto, Isao Kayano, Tomoyuki Yokogawa (OPU)
	14:15-14:25	Break ( 10 min. )
Thu, Jan 18 PM 14:25 - 15:25
(10) CPSY	14:25-15:25
	15:25-15:35	Break ( 10 min. )
Thu, Jan 18 PM Chair: Kazuya Tanigawa (Hiroshima City Univ.) 15:35 - 16:25
(11) RECONF	15:35-16:00
(12) RECONF	16:00-16:25	Integrated Machine Code Monitor on FPGA	Hiroaki Kaneko, Akinori Kanasugi (TokyoDenki Univ.)
	16:25-16:35	Break ( 10 min. )
Thu, Jan 18 PM Chair: Hiroki Nakahara (Tokyo Tech) 16:35 - 17:25
(13) RECONF	16:35-17:00		Daichi Tanaka, Antoniette Mondigo, Kentaro Sano, Satoru Yamamoto (Tohoku Univ)
(14) VLD	17:00-17:25	Distributed Memory Architecture for High-Level Synthesis from Erlang	Kagumi Azuma, Shoki Hamana, Hidekazu Wakabayashi, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuaki Yoshida, Hiroyuki Kanbara (ASTEM)
	17:25-18:00	Break ( 35 min. )
Thu, Jan 18 PM 18:00 - 20:00
	-
Fri, Jan 19 AM Chair: Kentaro Sano (Tohoku Univ.) 09:15 - 10:30
(15) RECONF	09:15-09:40	FPGA Implementation of Stencil Computation Using Multi-threading with High-level Synthesis Based on Java Language	Keitaro Yanai (TUAT), Yasunori Osana (Ryukyus Univ.), Hironori Nakajo (TUAT)
(16) RECONF	09:40-10:05	Overview of an HLS Framework Surpporting IoT/CPS Development	Daichi Teruya, Hironori Nakajo (TUAT)
(17) RECONF	10:05-10:30	Automatic Conversion from Snort PCRE to Verilog HDL	Masahiro Fukuda, Yasushi Inoguchi (JAIST)
	10:30-10:40	Break ( 10 min. )
Fri, Jan 19 AM 10:40 - 11:55
(18) VLD	10:40-11:05	Design and Implementation of 176-MHz WXGA 30-fps Real-time Optical Flow Processor	Satoshi Kanda, Yu Suzuki, Masato Ito (Nihon Univ.), Kousuke Imamura, Yoshio Matsuda (Kanazawa Univ.), Tetsuya Matsumura (Nihon Univ.)
(19) VLD	11:05-11:30	A study on the power efficiency of via-switch oriented programmable logic 0-1-A-~A LUT	Asuka Natsuhara, Takashi Imagawa, Hiroyuki Ochi (Ritsumeikan Univ.)
(20) RECONF	11:30-11:55	Total-ionizing-dose tolerance of an optically reconfigurable gate array	Takumi Fujimori, Minoru Watanabe (Shizuoka Univ.)
	11:55-13:00	Lunch Break ( 65 min. )
Fri, Jan 19 PM 13:00 - 14:15
(21) RECONF	13:00-13:25	FPGA accelerator of CNN using Power of 2 Approximation and Pruning weights	Takahiro Utsunomiya, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)
(22)	13:25-13:50
(23) CPSY	13:50-14:15	Accelerating Sequential Learning Algorithm OS-ELM Using FPGA-NIC	Mineto Tsukada, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
	14:15-14:25	Break ( 10 min. )
Fri, Jan 19 PM 14:25 - 15:40
(24) CPSY	14:25-14:50	Accelerating Serialization Protocols for Network-Attached FPGAs	Takuma Iwata, Koya Mitsuzuka, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani (Keio Univ.)
(25) RECONF	14:50-15:15
(26) RECONF	15:15-15:40	Circuit Partitioning for Stream Computing in Scalable Hardware Mechanism and its implementation on FPGAs	Yoshio Murata, Hironori Nakajo (TUAT)
	15:40-15:50	Break ( 10 min. )
Fri, Jan 19 PM 15:50 - 17:05
(27)	15:50-16:15
(28) VLD	16:15-16:40	Reinforcing Generation of Control Flow Statements in Random Test System of C Compilers Based on Equivalence Transformation	Mitsuyoshi Iwatsuji, Nagisa Ishiura (Kwansei Gakuin Univ.)
(29) VLD	16:40-17:05	Mutant Generation of Performance Tests for LLVM Back-Ends	Kenji Tanaka, Nagisa Ishiura (Kwansei Gakuin Univ.), Masanari Nishimura, Akiya Fukui (Renesas)

Announcement for Speakers
General Talk	Each speech will have 20 minutes for presentation and 5 minutes for discussion.

Contact Address and Latest Schedule Information
CPSY	Technical Committee on Computer Systems (CPSY) [Latest Schedule]
	Contact Address	Takashi Miyoshi (FUJITSU) TEL +81-44-754-2931, FAX +81-44-754-2672 E-: CPSY WEB http://www.ieice.or.jp/iss/cpsy/jpn/
VLD	Technical Committee on VLSI Design Technologies (VLD) [Latest Schedule]
	Contact Address	Shinobu Nagayama (Hiroshima City University) E-: s_-cu
	Announcement	See also VLD's homepage: http://www.ieice.org/~vld/
RECONF	Technical Committee on Reconfigurable Systems (RECONF) [Latest Schedule]
	Contact Address	Masato Motomura（Hokkaido Univ.） E-: isti Yuki Kobayashi (NEC) E-: y-bahqc
	Announcement	http://www.ieice.org/~reconf/
IPSJ-ARC	Special Interest Group on System Architecture (IPSJ-ARC) [Latest Schedule]
	Contact Address
IPSJ-SLDM	Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) [Latest Schedule]
	Contact Address	Yukio Mitsuyama (Kochi Univ. of Tech.) E-:o-
	Announcement	Please see the IPSJ-SLDM page below: http://www.sig-sldm.org/