| Conference Date |
Mon, Mar 4, 2013 13:50 - 17:00
Tue, Mar 5, 2013 10:00 - 16:50
Wed, Mar 6, 2013 10:30 - 16:00 |
| Topics |
Design Technology for System-on-Silicon |
| Conference Place |
|
| Transportation Guide |
http://www.okiseikan.or.jp/new/news.php |
Contact
Person |
Prof. Katsuhiko Shimabukuro |
Copyright
and
reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Mon, Mar 4 PM
13:50 - 15:05 |
| (1) |
13:50-14:15 |
A Logic Simplification Algorithm with Multiple Stuck-at Faults for Error Tolerant Application  VLD2012-136 |
Junpei Kamei, Shingo Matsuki, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) |
| (2) |
14:15-14:40 |
Acceleration of current-threshold determination toward on-line IDDQ testing through parameter estimation VLD2012-137 |
Michihiro Shintani, Takashi Sato (Kyoto Univ.) |
| (3) |
14:40-15:05 |
Self-Compensation of Manufacturing Variability using On-Chip Sensors VLD2012-138 |
Yuma Higuchi, Masanori Hashimoto, Takao Onoye (Osaka Univ.) |
| |
15:05-15:20 |
Break ( 15 min. ) |
Mon, Mar 4 PM
15:20 - 17:00 |
| (4) |
15:20-15:45 |
APR-based Legalization Method VLD2012-139 |
Shota Hirae, Maho Ishikawa, Yasuhiro Takashima (Univ. of Kitakyusyu) |
| (5) |
15:45-16:10 |
TSV-aware Analytical Placement VLD2012-140 |
Koji Morita, Yasuhiro Takashima (Univ. of Kitakyushu) |
| (6) |
16:10-16:35 |
Analytical Placement for Rectilinear Blocks VLD2012-141 |
Tomoaki Gotanda, Yasuhiro Takashima (Univ. of Kitakyusyu) |
| (7) |
16:35-17:00 |
The minimum perturbation placement realization for convex blocks VLD2012-142 |
Hiroki Matsugano, Shota Hirae, Yasuhiro Takashima (Univ. of Kitakyushu) |
Tue, Mar 5 AM
10:00 - 11:40 |
| (8) |
10:00-10:25 |
An Automatic Nested Loop Pipelining method from C level behavior description VLD2012-143 |
Masahiro Nambu, Takashi Kambe (Kinki Univ.) |
| (9) |
10:25-10:50 |
An Acceleration method and its evaluation for Coarse Grained Reconfigurable Circuit Synthesis VLD2012-144 |
Nobuyuki Araki, Takashi Kambe (Kinki Univ.) |
| (10) |
10:50-11:15 |
High Level Resynthesis Approach of Reusable RTL Property VLD2012-145 |
Msaato Tatsuoka, Mineo Kaneko (JAIST) |
| (11) |
11:15-11:40 |
A Multi-Task Scheduling and Allocation for Highly Reliable Network-on-Chip VLD2012-146 |
Hiroshi Saito (Univ. of Aizu), Tomohiro Yoneda (NII), Yuichi Nakamura (NEC) |
| |
11:40-13:00 |
Break ( 80 min. ) |
Tue, Mar 5 PM
13:00 - 13:50 |
| (12) |
13:00-13:50 |
[Invited Talk]
Cyber-Physical Systems and LSI Design Technologies VLD2012-147 |
Shinpei Kato, Masato Edahiro (Nagoya Univ.) |
| |
13:50-14:05 |
Break ( 15 min. ) |
Tue, Mar 5 PM
14:05 - 15:20 |
| (13) |
14:05-14:30 |
An Optimal Design Method for Input Signals of Small SoG-LCDs and Its Evaluation VLD2012-148 |
Taichi Suizu, Shuji Tsukiyama (Chuo Univ.) |
| (14) |
14:30-14:55 |
A Routing Method Considering Wirelength of Each Net for Single Layer PCB Routing VLD2012-149 |
Kyosuke Shinoda, Atsushi Takahashi (Tokyo Inst. of Tech.) |
| (15) |
14:55-15:20 |
A Parallel Global Routing Method Sharing Routing Regions for Multi-Core Processors VLD2012-150 |
Yasuhiro Shintani, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi (Hiroshima City Univ.) |
| |
15:20-15:35 |
Break ( 15 min. ) |
Tue, Mar 5 PM
15:35 - 16:50 |
| (16) |
15:35-16:00 |
[Memorial Lecture]
Line Sharing Cache: Exploring Cache Capacity with Frequent Line Value Locality VLD2012-151 |
Keitarou Oka, Hiroshi Sasaki, Koji Inoue (Kyushu Univ.) |
| (17) |
16:00-16:25 |
[Memorial Lecture]
An Adaptive Current-Threshold Determination for IDDQ Testing Based on Bayesian Process Parameter Estimation VLD2012-152 |
Michihiro Shintani, Takashi Sato (Kyoto Univ.) |
| (18) |
16:25-16:50 |
[Memorial Lecture]
Network Simplex Method Based Multiple Voltage Scheduling in Power-Efficient High-Level Synthesis VLD2012-153 |
Cong Hao, Song Chen, Takeshi Yoshimura (Waseda Univ.) |
Wed, Mar 6 AM
10:30 - 11:45 |
| (19) |
10:30-10:55 |
A worst-case-aware design methodology for oscillator-based true random number generator with stochastic behavior modeling VLD2012-154 |
Takehiko Amaki, Masanori Hashimoto (Osaka Univ.), Yukio Mitsuyama (Kochi Univ. of Tech.), Takao Onoye (Osaka Univ.) |
| (20) |
10:55-11:20 |
Design and Evalution of Sleep Control Circuit for Fine-grain Power Gating VLD2012-155 |
Yoshihiro Tsurui, Kimiyoshi Usami, Tatsunori Hashida, Tetsuya Muto, Yuki Shimada (Shibaura Inst. of Tech.) |
| (21) |
11:20-11:45 |
a design of COMET II processor as an embedded softcore processor VLD2012-156 |
Kei Kimoto, Tomonori Izumi (Ritsumeikan Univ.) |
| |
11:45-13:15 |
Break ( 90 min. ) |
Wed, Mar 6 PM
13:15 - 14:30 |
| (22) |
13:15-13:40 |
Delay Analysis of Reconvergent Paths with Correlation VLD2012-157 |
Masatsugu Hosoki, Hiroshi Sasaki, Yasuhiro Takashima (Univ. of Kitakyushu) |
| (23) |
13:40-14:05 |
A Delay Control Circuit with Channel Length Decomposition and Its Application VLD2012-158 |
Yuichi Toyota, Yuki Nakashima, Toru Fujimura, Shigetoshi Nakatake (Univ of Kitakyushu) |
| (24) |
14:05-14:30 |
Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning VLD2012-159 |
Mineo Kaneko (JAIST) |
| |
14:30-14:45 |
Break ( 15 min. ) |
Wed, Mar 6 PM
14:45 - 16:00 |
| (25) |
14:45-15:10 |
Probability Driven Hierarchical Fault Analysis System and its Implementation VLD2012-160 |
Hikaru Goto, Masaya Yoshikawa (Meijo Univ.) |
| (26) |
15:10-15:35 |
Trojan Circuit for Fault Analysis Countermeasure and its Implementation VLD2012-161 |
Takaya Tsukadaira, Daisuke Matsushima (Meijo Univ.), Takeshi Kumaki (Ritsumeikan Univ.), Masaya Yoshikawa (Meijo Univ.) |
| (27) |
15:35-16:00 |
Robust Redundant Circuit Structure to Mitigate Wearout by Reversing Register Values VLD2012-162 |
Shogo Okada, Masaki Masuda (Kyoto Inst. of Tech.), Jun Yao, Hajime Shimada (NAIST), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) |
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