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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Toshinori Sueyoshi Vice Chair: Akira Nagoya, Tomomi Sato
Secretary: Tetsuo Hironaka, Yuichiro Shibata
Assistant: Masahiro Iida

DATE:
Wed, Nov 30, 2005 14:40 - 17:25
Thu, Dec 1, 2005 09:30 - 16:40
Fri, Dec 2, 2005 09:30 - 12:15

PLACE:
The Kitakyushu International Conference Center(3-9-30, Asano, Kokurakita-ku, Kitakyushu-shi, 802-0001 Japan.http://www.kitakyu-cb.jp/en/f_acs.html. Dr. Yuichiro Shibata (Nagasaki Univ.). 095-819-2572)

TOPICS:

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Wed, Nov 30 PM Architectures I (14:40 - 15:55)
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(1) 14:40 - 15:05
Variable Grain Logic Cell Architecture for Reconfigurable Device
Motoki Amagasaki, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

(2) 15:05 - 15:30
Implementation of Basic Function Blocks for Variable Grain Logic Cell
Naoto Hamabe, Hideaki Nakayama, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

(3) 15:30 - 15:55
A study of reconfigurable hardware architecture for physical layer of wireless access systems
Yoshio Wada (Samsung Yokohama Research Institute)

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Wed, Nov 30 PM Applications I (16:10 - 17:25)
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(4) 16:10 - 16:35
Implementation of 1-D/2-D FFT on the Dynamically Reconfigurable Processor DAPDNA-2
Kosuke Shiba, Atsushi Imaizumi, Takeshi Sakuma (IPFlex)

(5) 16:35 - 17:00
Adaptive Computling on the Dynamically Reconfigurable Processor DRP-1
Shohei Abe, Yohei Hasegawa (Keio Univ.), Takao Toi, Takeshi Inuo (NEC System Devices Research Labs.), Hideharu Amano (Keio Univ.)

(6) 17:00 - 17:25
A New Design Method for Implementing Real-Time Embedded Systems on Dynamically Reconfigurable Processors
Ryo Nakahashi, Tomoya Kitani (Osaka Univ.), Keiichi Yasumoto (NAIST), Akio Nakata, Teruo Higashino (Osaka Univ.)

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Thu, Dec 1 AM Networks (09:30 - 10:45)
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(7) 09:30 - 09:55
A Study on Shortest Path Routing Algorithm on Reconfigurable Processor
Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka (Keio Univ.), Kosuke Shiba (IPFlex)

(8) 09:55 - 10:20
Design of an application layer processing engine using dynamic reconfiguration
Yutaka Sugawara, Mary Inaba, Kei Hiraki (Univ. Tokyo)

(9) 10:20 - 10:45
A solution for perfect classified networks
Charlotte Roesener, Hidetaka Kojou, Hiroaki Nishi (Keio Univ.)

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Thu, Dec 1 AM Security and dependability (11:00 - 12:15)
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(10) 11:00 - 11:25
Anomaly Detection Mechanism installed in Dynamic Reconfigurable Processor
Takashi Isobe, Shinji Nishimura (Hitachi)

(11) 11:25 - 11:50
Proposal of a virus check system using FPGA
Kei Shimane (Toho Univ.), Yosuke Iijima (Univ. Of Tsukuba), Eiichi Takahashi (AIST), Tatsumi Furuya (Toho Univ.), Tetsuya Higuchi (AIST)

(12) 11:50 - 12:15
Permanent Fault Detection for FPGA by Reconfiguration
Yousuke Nakamura, Kei Hiraki (Tokyo Univ.)

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Thu, Dec 1 PM Architectures II (13:30 - 15:10)
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(13) 13:30 - 13:55
Architecture Overview of Reconfigurable Processor FE-GA for Digital Media Processing
Takanobu Tsunoda, Masashi Takada, Yohei Akita, Hiroshi Tanaka, Makoto Satoh, Masaki Ito (Hitachi)

(14) 13:55 - 14:20
Performance/Area Improvement of Reconfigurable Processor EF-GA by Hierarchical Memory Control of Configuration Data
Masashi Takada, Takanobu Tsunoda, Yohei Akita, Hiroshi Tanaka, Makoto Satoh, Masaki Ito (Hitachi)

(15) 14:20 - 14:45
Study of Audio Software on Reconfigurable Processor "FE-GA"
Hiroshi Tanaka, Takanobu Tsunoda, Yohei Akita, Masashi Takada, Masaki Ito, Makoto Satoh (Hitachi)

(16) 14:45 - 15:10
Mapping of FFT onto Reconfigurable Processor FE-GA
Makoto Satoh, Hiroshi Tanaka, Takanobu Tsunoda, Masashi Takada, Yohei Akita, Masaki Ito (Hitachi, Ltd.)

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Thu, Dec 1 PM Applications II (15:25 - 16:40)
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(17) 15:25 - 15:50
FPGA implementation of H.264/AVC encoder using soft processor core
Yutaka Okamoto, Keisuke Iwai, Takakazu Kurokawa (NDA)

(18) 15:50 - 16:15
Motion controller on a reconfigurable device for birateral forceps robots
Ena Ishii, Hiroaki Nishi, Kouhei Ohnishi (Keio Univ.)

(19) 16:15 - 16:40
A Study of The High-Speed Reconfigurable System for The Object Recognition
Hiroshi Kadota, Shingo Kasaki (Kyushu Univ.), Akiyoshi Wakatani (Konan Univ.)

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Fri, Dec 2 AM Hardware Management (09:30 - 10:20)
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(20) 09:30 - 09:55
Development of a Reconfiguration Management Mechanism for Dynamically Reconfigurable System
Takanori Susaki, Isao Sakamoto, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

(21) 09:55 - 10:20
Online FPGA Placement under I/O Timing Constraints
Mitsuru Tomono, Masaki Nakanishi, Shigeru Yamashita, Katsumasa Watanabe (NAIST)

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Fri, Dec 2 AM Acceleration Techniques (11:00 - 12:15)
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(22) 11:00 - 11:25
Prototyping and Evaluation of PCI Express Module for PGR System
Tsuyoshi Hamada (RIKEN), Yuichi Okuyama (Univ Aizu), Naohito Nakasato (RIKEN)

(23) 11:25 - 11:50
Evaluation of Reconfigurable and Highly Functional Memory Controller
Toshiharu Imai, Kiyofumi Tanaka (JAIST)

(24) 11:50 - 12:15
Development of an FPGA Board toward Reconfigurable Cluster Computing
Kazuto Hewa, Tomohiro Okajima, Hidetomo Shibamura, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

# Information for speakers
General Talk will have 20 minutes for presentation and 5 minutes for discussion.

=== Technical Committee on Reconfigurable Systems (RECONF) ===
# FUTURE SCHEDULE:

Tue, Jan 17, 2006 - Wed, Jan 18, 2006: [Tue, Nov 15], Topics: FPGA and its Application, etc.

# SECRETARY:
Masahiro IIDA (Kumamoto Univ.)
E-mail: ii