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Technical Committee on Reconfigurable Systems (RECONF)
Chair: Toshinori Sueyoshi Vice Chair: Akira Nagoya, Tomomi Sato
Secretary: Tetsuo Hironaka, Yuichiro Shibata
Assistant: Masahiro Iida

DATE:
Thu, May 18, 2006 11:00 - 18:00
Fri, May 19, 2006 10:00 - 16:15

PLACE:
(http://www.tohoku.ac.jp/english/map/location.html)

TOPICS:
Reconfigurable Systems, etc.

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Thu, May 18 AM (11:00 - 12:00)
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(1) 11:00 - 11:30
A Study of Mapping Method for Variable Grain Logic Cell Architecture
Ryoichi Yamaguchi, Kazunori Matsuyama, Hideaki Nakayama, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.)

(2) 11:30 - 12:00
A Retargetable Compiler for Cell-Array Based Self-Reconfigurable Architecture
Masayuki Hiromoto, Shin'ichi Kouyama, Kentaro Nakahara, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura (Kyoto Univ.)

----- Lunch Break ( 60 min. ) -----

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Thu, May 18 PM (13:00 - 14:00)
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(3) 13:00 - 14:00
[Special Invited Talk]
Three-Dimensional Integration Technology and Reconfigurable 3D-SoC
Mitsumasa Koyanagi, Takeaki Sugimura, Takafumi Fukushima, Tetsu Tanaka (Tohoku Univ.)

----- Break ( 15 min. ) -----

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Thu, May 18 PM (14:15 - 15:45)
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(4) 14:15 - 14:45
Detail Analysis of Optimal Body Bias Voltage Set for Flex Power FPGA
Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST)

(5) 14:45 - 15:15
Reconfigurable Architectures with On-chip Networks for Multitask Designs
Yohei Hasegawa, Hiroki Matsutani (Keio Univ.), Michihiro Koibuchi (NII), Hideharu Amano (Keio Univ.)

(6) 15:15 - 15:45
A performance evaluation of Matrix Processing Engine for media applications
Takayuki Oono (Kumamoto Univ.), Hiroyuki Yamasaki (Renesas Tech.), Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)

----- Break ( 15 min. ) -----

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Thu, May 18 PM (16:00 - 18:00)
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(7) 16:00 - 16:30
Low Power Design Technique on Dynamic Reconfigurable Processor
Takashi Nishimura, Yohei Hasegawa, Hideharu Amano (Keio Univ.)

(8) 16:30 - 17:00
Functional Devided Implementation of Video Application on Dynamic Reconfigurable Processor
Takuro Nakamura, Hideharu Amano, Yohei Hasegawa (Keio Univ.), Osamu Toyama (Mitsubishi Electric)

(9) 17:00 - 17:30
Implementation of Multiplication over Finite Fields in Characteristic Two on Dynamically Reconfigurable Processor
Hideyuki Tsuchiya, Miwa Miyata, Yuichiro Shibata, Ryuichi Harasawa, Kiyoshi Oguri (Nagasaki Univ.)

(10) 17:30 - 18:00
Implementation and Evaluation of General-Purpose Host Interface on ReCSiP Board
Toshinori Kojima, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.)

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Fri, May 19 AM (10:00 - 12:00)
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(11) 10:00 - 10:30
Reconfigurable Sensor Network Based on Mutual Communications with Reliability Index
Takeshi Fujiwara, Hiroyuki Takahashi, Masaharu Nakazawa (Univ. Tokyo), Yoshiki Shimomura (Tokyo Metro. Univ.), Shi Boxuan (Univ. Tokyo)

(12) 10:30 - 11:00
Discussion on Building of Acoustic Field Simulation System with FPGA
Eiko Sugawara, Yasushi Inoguchi (JAIST), Takao Tsuchiya (Doshisha Univ.), Yasushi Hibino (JAIST)

(13) 11:00 - 11:30
FPGA-based Processor for Computational Fluid Dynamics
Takanori Iizuka, Kentaro Sano, Satoru Yamamoto (Tohoku Univ.)

(14) 11:30 - 12:00
Speed enhancement of FPGAs by reconfigration utilizing variations within a chip
Kosuke Ogata, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera (Kyoto Univ.)

----- Lunch Break ( 60 min. ) -----

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Fri, May 19 PM (13:00 - 14:00)
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(15) 13:00 - 14:00
[Special Invited Talk]
Wafer Scale Integration and Reconfigurable Systems
Susumu Horiguchi (Tohoku Univ)

----- Break ( 15 min. ) -----

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Fri, May 19 PM (14:15 - 16:15)
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(16) 14:15 - 14:45
An FPGA Implementation of 200Mbps CI/OFDM Tranceiver
Tomonori Izumi (Ritsumeikan Univ.), Minoru Okada (NAIST), Yosuke Yamahara, Yuki Matsumoto, Takayuki Nakatani, Naoto Umehara, Shoichiro Namba, Masahiro Funatsuki, Minoru Sakaida (Ritsumeikan Univ.), Toshihiro Masaki (Osaka Univ.)

(17) 14:45 - 15:15
An FPGA Implementation of digital modulator of High-Speed CI/OFDM Tranceiver
Naoto Umehara, Yuki Matsumoto, Takayuki Nakatani, Tomonori Izumi (Ritsumeikan Univ.), Minoru Okada (NAIST), Toshihiro Masaki (Osaka Univ.)

(18) 15:15 - 15:45
An FPGA Implementation of Digital Synchronizers of High-Speed CI/OFDM Tranceiver
Takayuki Nakatani, Shoichiro Namba, Masahiro Funatsuki, Tomonori Izumi (Ritsumeikan Univ.), Minoru Okada (NAIST), Toshihiro Masaki (Osaka Univ.)

(19) 15:45 - 16:15
A Platform for FPGA Prototyping of High-Speed CI/OFDM Tranceiver
Yosuke Yamahara, Yuki Matsumoto (Ritsumeikan Univ.), Toshihiro Masaki (Osaka Univ.), Tomonori Izumi (Ritsumeikan Univ.), Minoru Okada (NAIST), Kenji Fujita, Kenji Matsumura (KCS)

# Information for speakers
General Talk will have 25 minutes for presentation and 5 minutes for discussion.
Special Invited Talk will have 50 minutes for presentation and 10 minutes for discussion.

=== Technical Committee on Reconfigurable Systems (RECONF) ===

# SECRETARY:
Masahiro IIDA (Kumamoto Univ.)
E-mail: ii