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=============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Akira Onozawa (NTT) Vice Chair: Kimiyoshi Usami (Shibaura Inst. of Tech.) Secretary: Akihisa Yamada (Sharp), Kazutoshi Kobayashi (Kyoto Inst. of Tech.) =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Kazutoshi Wakabayashi Secretary: Naohito Kojima, Hiroaki Komatsu, Nozomu Togawa DATE: Wed, May 18, 2011 14:15 - 17:50 Thu, May 19, 2011 09:30 - 14:35 PLACE: Kitakyushu International Conference Center(http://www.convention-a.jp/access/. Prof. Yasuhiro Takashima. +81-93-695-3729) TOPICS: System Design, etc. ---------------------------------------- Wed, May 18 PM (14:15 - 15:30) ---------------------------------------- (1)/VLD 14:15 - 14:40 Study of the slew-rate contorol system for reducing far-end crosstalk Kazunori Nakashima, Suguru Kato, Shinichi Sasaki (Saga Univ) (2)/VLD 14:40 - 15:05 An Effective Overlap Removable Objective for Analytical Placement Syota Kuwabara, Yukihide Kohira (Univ. of Aizu), Yasuhiro Takashima (Univ. of Kitakyushu) (3)/VLD 15:05 - 15:30 Path Encoding Method for High Speed Frequency-Mapping Associative Memory Seiryu Sasaki, Masahiro Yasuda, Akio Kawabata, Tetsushi Koide, Hans Juergen Mattausch (Hiroshima Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, May 18 PM (15:45 - 16:45) ---------------------------------------- (4)/VLD 15:45 - 16:45 [Invited Talk] Recent Gating-Techniques for Power Reduction Kimiyoshi Usami (Shibaura Inst. of Tech.) ----- Break ( 5 min. ) ----- ---------------------------------------- Wed, May 18 PM (16:50 - 17:50) ---------------------------------------- (5)/VLD 16:50 - 17:50 [Invited Talk] Low Power Design Technology on Algorithm/Architecture Level for Video Processing Satoshi Goto (Waseda Univ.) ---------------------------------------- Thu, May 19 AM (09:30 - 10:45) ---------------------------------------- (6)/VLD 09:30 - 09:55 Super-resolution by UsingWeighted Adders with Selector Logics Hiromine Yoshihara, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa (Waseda Univ.) (7)/VLD 09:55 - 10:20 Multi-Stage Power Gating Based on Controlling Values of Logic Gates Jin Yu, Shinji Kimura (Waseda Univ.) (8) 10:20 - 10:45 ----- Break ( 10 min. ) ----- ---------------------------------------- Thu, May 19 AM (10:55 - 12:10) ---------------------------------------- (9) 10:55 - 11:20 (10) 11:20 - 11:45 (11) 11:45 - 12:10 ----- Lunch Break ( 70 min. ) ----- ---------------------------------------- Thu, May 19 PM (13:20 - 14:35) ---------------------------------------- (12) 13:20 - 13:45 (13) 13:45 - 14:10 (14) 14:10 - 14:35 # Information for speakers General Talk will have 20 minutes for presentation and 5 minutes for discussion. === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Thu, Jun 30, 2011 - Fri, Jul 1, 2011: Okinawa-Ken-Seinen-Kaikan [Fri, Apr 8] # SECRETARY: Akihisa Yamada (Sharp) E-mail:     a    s rp Tel: +81-743-65-2531, Fax: +81-743-65-0554 # ANNOUNCEMENT: # See also VLD's homepage: http://www.ieice.org/~vld/ === Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === # FUTURE SCHEDULE: Sat, Jul 2, 2011 - Sun, Jul 3, 2011 (tentative): [Thu, May 19] Last modified: 2011-05-16 11:31:06 |
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