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=============================================== Technical Committee on Reconfigurable Systems (RECONF) Chair: Toshinori Sueyoshi Vice Chair: Akira Nagoya, Tomomi Sato Secretary: Tetsuo Hironaka, Yuichiro Shibata Assistant: Masahiro Iida =============================================== Technical Committee on VLSI Design Technologies (VLD) Chair: Shinji Kimura Vice Chair: Hirofumi Hamamura Secretary: Yusuke Matsunaga, Toshiyuki Shibuya =============================================== Technical Committee on Computer Systems (CPSY) Chair: Takanobu Baba Vice Chair: Nobuki Kajihara, Toshinori Sueyoshi Secretary: Hiroko Midorikawa, Akira Asato Assistant: Takashi Yokota =============================================== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) Chair: Takashi Kambe Secretary: Masato Edahiro, Mitsuhisa Ohnishi, Kiyoharu Hamaguchi DATE: Tue, Jan 17, 2006 13:00 - 18:00 Wed, Jan 18, 2006 10:00 - 16:10 PLACE: (Prof. Hideharu Amano. 045-560-1063) TOPICS: FPGA and its Application, etc. ---------------------------------------- Tue, Jan 17 PM (13:00 - 14:40) ---------------------------------------- (1) 13:00 - 13:25 Implimentation of high speed audiofingerprint system using FPGAs Hisashi Isonaga, Yasushi Inoguchi (JAIST) (2) 13:25 - 13:50 Voice Recognition LSI based on FTTSS Tomotaka Nakano, Park Hu Gang, Tetsuo Funada, Akio Kitagawa (Kanazawa Univ) (3) 13:50 - 14:15 An LSI design to support Sound Finite Difference Time Domain Method Daichi Ito, Ryotaro Kobayashi, Toshio Shimada (Nagoya Univ.) (4) 14:15 - 14:40 Accelaration of Hydrosynamical Simulations using a FPGA board Naohito Nakasato, Tsuyoshi Hamada (RIKEN) ----- Break ( 20 min. ) ----- ---------------------------------------- Tue, Jan 17 PM (15:00 - 16:15) ---------------------------------------- (5) 15:00 - 15:25 Programmable Numerical Function Generators Based on Quadratic Approximation: Architecture and Synthesis Method Shinobu Nagayama (Hiroshima City Univ.), Tsutomu Sasao (K.I..T.), Jon T. Butler (Naval Postgraduate School) (6) 15:25 - 15:50 Implementation of Stream Application on Programmable Devices by C Level Design Naohiro Katsura, Yohei Hasegawa, Vu Manh Tuan, Takamasa Kanamori, Hideharu Amano (Keio Univ.) (7) 15:50 - 16:15 Multuiple Programming Method and Circuit Design for a Phase Change Nonvolatile Random Access Memory Takatomi Izumi, Masashi Takata, Kazuya Nakayama, Akio Kitagawa (Kanazawa Univ.) ----- Break ( 15 min. ) ----- ---------------------------------------- Tue, Jan 17 PM (16:30 - 18:00) ---------------------------------------- (8) 16:30 - 16:55 Modification of monotonic route to reduce max density for single layer BGA package Yoshitaka Nomura, Atsushi Takahashi (Tokyo Tech) (9) 16:55 - 17:20 Boolean Equivalence Checking Using a Subset of First-Order Logic Atsushi Moritomo, Kiyoharu Hamaguchi, Toshinobu Kashiwabara (Osaka Univ.) ----- Break ( 40 min. ) ----- ---------------------------------------- Wed, Jan 18 AM (10:00 - 11:40) ---------------------------------------- (10) 10:00 - 10:25 Optimization of Body Bias Voltage Set for Threshold Voltage Control in Flex Power FPGA Takashi Kawanami, Masakazu Hioki, Yohei Matsumoto (AIST), Toshiyuki Tsutsumi (AIST/MEIJI), Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike (AIST) (11) 10:25 - 10:50 A Study of the Dynamically Reconfigurable Processor Vulcan Toshihiko Hashinaga (Kyushu Univ.), Lovic Gauthier, Takayuki Kando, Victor Mauro Goulart Ferreira, Ryutaro Susukita (FLEETS), Tetsuo Hiraki, Yosuke Yamazaki, Takaaki Nagano, Kazuaki Murakami (Kyushu Univ.) (12) 10:50 - 11:15 The direct execution mode on dynamically reconfigurable processors Hideharu Amano, Yohei Hasegawa, Shohei Abe (Keio Univ.) (13) 11:15 - 11:40 A Study on Resource Sharing Technique for Multi-Context Logic Device Hiroshi Shinohara, Masaki Kobata, Shigeki Imai, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) ----- Lunch Break ( 80 min. ) ----- ---------------------------------------- Wed, Jan 18 PM (13:00 - 14:15) ---------------------------------------- (14) 13:00 - 13:25 The Proposal and Verification of FPGA Remote-Reconfiguration Hiroshi Tanno, Hiroshi Tsubokawa (Tokyo University of Technology) (15) 13:25 - 13:50 Implementation and Evaluation of Remote Logic Analyzer Go Saitou, Kazuo Nagata, Hideo Harada, Hidetomo Shibamura, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) (16) 13:50 - 14:15 Retargeting GCC and GNU Toolchain for Extended Instruction Set Yuji Nagamatsu, Nagisa Ishiura (Kwansei Gakuin Univ.), Nobuyuki Hikichi (SRA-KTL) ----- Break ( 15 min. ) ----- ---------------------------------------- Wed, Jan 18 PM (14:30 - 16:10) ---------------------------------------- (17) 14:30 - 14:55 A Parallel Volume Rendering System implemented with High-Speed DVI Link Dai Okamura, Yusuke Noda, Shinobu Miwa, Hajime Shimada (Kyoto Univ), Yasuhiko Nakashima (Kyoto Univ/JST), Shin-ichiro Mori, Shinji Tomita (Kyoto Univ) (18) 14:55 - 15:20 A Stochastic Biochemical Simulator with a Data-transfer Network on an FPGA Masato Yoshimi, Yasunori Osana, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) (19) 15:20 - 15:45 A Performance Improvement Strategy for Numerical Integration on an FPGA-Based Biochemical Simulator ReCSiP Yuri Nishikawa, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Toshinori Kojima (Keio Univ.), Akira Funahashi, Noriko Hiroi (JST), Yuichiro Shibata, Naoki Iwanaga (Nagasaki Univ.), Hiroaki Kitano (JST), Hideharu Amano (Keio Univ.) (20) 15:45 - 16:10 Hardware-resource Utilization Analysis on an FPGA-Based Biochemical Simulator ReCSiP Yasunori Osana (Keio Univ.), Naoki Iwanaga (Nagasaki Univ.), Masato Yoshimi, Yow Iwaoka, Toshinori Kojima, Yuri Nishikawa (Keio Univ.), Akira Funahashi (JST), Noriko Hiroi (Keio Univ.), Yuichiro Shibata, Hiroaki Kitano (Nagasaki Univ.), Hideharu Amano (Keio Univ.) === Technical Committee on Reconfigurable Systems (RECONF) === # SECRETARY: Masahiro IIDA (Kumamoto Univ.) E-mail: ii         -u TEL: +81-96-342-3649 FAX: +81-96-342-3649 === Technical Committee on VLSI Design Technologies (VLD) === # FUTURE SCHEDULE: Thu, Mar 9, 2006 - Fri, Mar 10, 2006: [Mon, Dec 26] # SECRETARY: Yusuke Matsunaga (Kyushu University) TEL +81-92-583-7621, FAX +81-92-583-1338 E-mail:    ccek shu-u# ANNOUNCEMENT: # You will see the latest information at the below WEB page. http://www.ieice.org/vld/index.html === Technical Committee on Computer Systems (CPSY) === # FUTURE SCHEDULE: Fri, Apr 14, 2006: Takeda Hall [Fri, Feb 10] # SECRETARY: Takashi Yokota (Utsunomiya Univ.) TEL +81-28-689-6290, FAX +81=28-689-6290 E-mail:    isu   -u=== Special Interest Group on System and LSI Design Methodology (IPSJ-SLDM) === Last modified: 2005-11-21 16:14:31 |
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